https://github.com/torvalds/linux
Revision f8577fb3c273bcae821a5254c8fbcf82016d9a8d authored by Chris Wilson on 19 November 2018, 15:41:53 UTC, committed by Joonas Lahtinen on 21 November 2018, 07:32:08 UTC
Under moderate amounts of GPU stress, we can observe on Bearlake and
Pineview (later gen3 models) that we execute the following batch buffer
before the write into the batch is coherent. Adding extra (tested with
upto 32x) MI_FLUSH to either the invalidation, flush or both phases does
not solve the incoherency issue with the relocations, but emitting the
MI_STORE_DWORD_IMM twice does. So be it.
Fixes: 7dd4f6729f92 ("drm/i915: Async GPU relocation processing")
Testcase: igt/gem_tiled_fence_blits # blb/pnv
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181119154153.15327-1-chris@chris-wilson.co.uk
(cherry picked from commit 7fa28e146994da1e8a4124623d7da97b798ea520)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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History 
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Tip revision: f8577fb3c273bcae821a5254c8fbcf82016d9a8d authored by Chris Wilson on 19 November 2018, 15:41:53 UTC
drm/i915: Write GPU relocs harder with gen3
drm/i915: Write GPU relocs harder with gen3
Tip revision: f8577fb
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| .clang-format | -rw-r--r-- | 12.7 KB |
| .cocciconfig | -rw-r--r-- | 59 bytes |
| .get_maintainer.ignore | -rw-r--r-- | 31 bytes |
| .gitattributes | -rw-r--r-- | 30 bytes |
| .gitignore | -rw-r--r-- | 1.5 KB |
| .mailmap | -rw-r--r-- | 10.5 KB |
| COPYING | -rw-r--r-- | 423 bytes |
| CREDITS | -rw-r--r-- | 96.5 KB |
| Kbuild | -rw-r--r-- | 2.2 KB |
| Kconfig | -rw-r--r-- | 563 bytes |
| MAINTAINERS | -rw-r--r-- | 470.7 KB |
| Makefile | -rw-r--r-- | 59.7 KB |
| README | -rw-r--r-- | 727 bytes |
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