https://github.com/torvalds/linux
Revision f91e2c3bd427239c198351f44814dd39db91afe0 authored by Catalin Marinas on 07 December 2010, 15:52:04 UTC, committed by Russell King on 12 December 2010, 23:25:58 UTC
The current implementation of the dcache_line_size macro reads the L1
cache size from the CCSIDR register. This, however, is not guaranteed to
be the smallest cache line in the cache hierarchy. The patch changes to
the macro to use the more architecturally correct CTR register.

Reported-by: Kevin Sapp <ksapp@quicinc.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1 parent 6313e3c
History
Tip revision: f91e2c3bd427239c198351f44814dd39db91afe0 authored by Catalin Marinas on 07 December 2010, 15:52:04 UTC
ARM: 6527/1: Use CTR instead of CCSIDR for the D-cache line size on ARMv7
Tip revision: f91e2c3
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