https://github.com/torvalds/linux
Revision fb5bbae9b1333d44023713946fdd28db0cd85751 authored by Chris Wilson on 05 November 2018, 09:43:05 UTC, committed by Joonas Lahtinen on 12 November 2018, 15:07:12 UTC
Exercising the gpu reloc path strenuously revealed an issue where the updated relocations (from MI_STORE_DWORD_IMM) were not being observed upon execution. After some experiments with adding pipecontrols (a lot of pipecontrols (32) as gen4/5 do not have a bit to wait on earlier pipe controls or even the current on), it was discovered that we merely needed to delay the EMIT_INVALIDATE by several flushes. It is important to note that it is the EMIT_INVALIDATE as opposed to the EMIT_FLUSH that needs the delay as opposed to what one might first expect -- that the delay is required for the TLB invalidation to take effect (one presumes to purge any CS buffers) as opposed to a delay after flushing to ensure the writes have landed before triggering invalidation. Testcase: igt/gem_tiled_fence_blits Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@vger.kernel.org Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181105094305.5767-1-chris@chris-wilson.co.uk (cherry picked from commit 55f99bf2a9c331838c981694bc872cd1ec4070b2) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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Tip revision: fb5bbae9b1333d44023713946fdd28db0cd85751 authored by Chris Wilson on 05 November 2018, 09:43:05 UTC
drm/i915/ringbuffer: Delay after EMIT_INVALIDATE for gen4/gen5
drm/i915/ringbuffer: Delay after EMIT_INVALIDATE for gen4/gen5
Tip revision: fb5bbae
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