swh:1:snp:3830a2898d2ae1f1288160960b86476be36082c7
Tip revision: 2fc41ae4889c7e0f39a01bd8d4ba2581698ddafb authored by Damien Couroussé on 31 March 2016, 15:58:11 UTC
initial import
initial import
Tip revision: 2fc41ae
CPU-areas.tex
\begin{table}
\begin{center}
\caption{Abbreviation of the simulated core designs and CPU areas}
\label{tab:auto-tun-sim-core-abbr}
\begin{tabular}{|l|c|c|c|c|c|c|}
\hline
\monocol{|c|}{\multirow{2}{*}{Abbrev.}}
& \multirow{2}{*}{Width}
& \multirow{2}{*}{Type}
& \multirow{2}{*}{VPUs}
& \multicolumn{3}{c|}{Area (\SI{}{\square\milli\meter})} \\ \cline{5-7}
& & & & Core & L2 & Total \\ \hline \hline
SI-I1 & 1 & IO & 1 & 0.45 & 1.52 & 1.97 \\ \hline
TI-I1 & 3 & IO & 1 & 1.81 & 5.88 & 7.70 \\ \hline
TI-I2 & 3 & IO & 2 & 2.89 & 5.88 & 8.78 \\ \hline
DI-I1 & 2 & IO & 1 & 1.00 & 3.19 & 4.19 \\ \hline
TI-I3 & 3 & IO & 3 & 3.98 & 5.88 & 9.86 \\ \hline
DI-I2 & 2 & IO & 2 & 1.48 & 3.19 & 4.67 \\ \hline
TI-O1 & 3 & OOO & 1 & 2.08 & 5.88 & 7.97 \\ \hline
DI-O1 & 2 & OOO & 1 & 1.15 & 3.19 & 4.34 \\ \hline
TI-O2 & 3 & OOO & 2 & 3.21 & 5.88 & 9.10 \\ \hline
DI-O2 & 2 & OOO & 2 & 1.67 & 3.19 & 4.86 \\ \hline
TI-O3 & 3 & OOO & 3 & 4.35 & 5.88 & 10.2 \\ \hline
\end{tabular}
\end{center}
\end{table}