swh:1:snp:c3bf2749e3476071fa748f67b0ffa2fdc5fe49d9
- v6.0-rc5
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- v6.0-rc3
- v6.0-rc2
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- v5.9-rc8
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- v5.7
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- v5.17-rc6
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- v5.17-rc1
- v5.17
- v5.16-rc8
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- v5.15-rc6
- v5.15-rc5
- v5.15-rc4
- v5.15-rc3
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- v5.15-rc1
- v5.15
- v5.14-rc7
- v5.14-rc6
- v5.14-rc5
- v5.14-rc4
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- v5.14-rc1
- v5.14
- v5.13-rc7
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- v5.13-rc5
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- v5.13-rc2
- v5.13-rc1
- v5.13
- v5.12-rc8
- v5.12-rc7
- v5.12-rc6
- v5.12-rc5
- v5.12-rc4
- v5.12-rc3
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- v5.12
- v5.11-rc7
- v5.11-rc6
- v5.11-rc5
- v5.11-rc4
- v5.11-rc3
- v5.11-rc2
- v5.11-rc1
- v5.11
- v5.10-rc7
- v5.10-rc6
- v5.10-rc5
- v5.10-rc4
- v5.10-rc3
- v5.10-rc2
- v5.10-rc1
- v5.10
- v5.1-rc7
- v5.1-rc6
- v5.1-rc5
- v5.1-rc4
- v5.1-rc3
- v5.1-rc2
- v5.1-rc1
- v5.1
- v5.0-rc8
- v5.0-rc7
- v5.0-rc6
- v5.0-rc5
- v5.0-rc4
- v5.0-rc3
- v5.0-rc2
- v5.0-rc1
- v5.0
- v4.9-rc8
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- v4.9-rc6
- v4.9-rc5
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- v4.9
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- v4.8-rc6
- v4.8-rc5
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- v4.8-rc2
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- v4.8
- v4.7-rc7
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- v4.7-rc5
- v4.7-rc4
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- v4.7-rc2
- v4.7-rc1
- v4.7
- v4.6-rc7
- v4.6-rc6
- v4.6-rc5
- v4.6-rc4
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- v4.6-rc2
- v4.6-rc1
- v4.6
- v4.5-rc7
- v4.5-rc6
- v4.5-rc5
- v4.5-rc4
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- v4.5-rc2
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- v4.5
- v4.4-rc8
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- v4.4-rc5
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- v4.4-rc3
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- v4.4
- v4.3-rc7
- v4.3-rc6
- v4.3-rc5
- v4.3-rc4
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- v4.3-rc2
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- v4.3
- v4.20-rc7
- v4.20-rc6
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- v4.20
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- v4.2-rc5
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- v4.2
- v4.19-rc8
- v4.19-rc7
- v4.19-rc6
- v4.19-rc5
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- v4.17-rc5
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- v4.17
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- v4.16-rc5
- v4.16-rc4
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- v4.16
- v4.15-rc9
- v4.15-rc8
- v4.15-rc7
- v4.15-rc6
- v4.15-rc5
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- v4.15
- v4.14-rc8
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- v4.14-rc6
- v4.14-rc5
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- v4.14-rc1
- v4.14
- v4.13-rc7
- v4.13-rc6
- v4.13-rc5
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- v4.13-rc2
- v4.13-rc1
- v4.13
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- v4.12-rc6
- v4.12-rc5
- v4.12-rc4
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- v4.12-rc1
- v4.12
- v4.11-rc8
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- v4.11-rc6
- v4.11-rc5
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- v4.11-rc1
- v4.11
- v4.10-rc8
- v4.10-rc7
- v4.10-rc6
- v4.10-rc5
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- v4.10-rc2
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- v4.1-rc8
- v4.1-rc7
- v4.1-rc6
- v4.1-rc5
- v4.1-rc4
- v4.1-rc3
- v4.1-rc2
- v4.1-rc1
- v4.1
- v4.0-rc7
- v4.0-rc6
- v4.0-rc5
- v4.0-rc4
- v4.0-rc3
- v4.0-rc2
- v4.0-rc1
- v4.0
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- v3.9-rc6
- v3.9-rc5
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- v3.9-rc3
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- v3.9-rc1
- v3.9
- v3.8-rc7
- v3.8-rc6
- v3.8-rc5
- v3.8-rc4
- v3.8-rc3
- v3.8-rc2
- v3.8-rc1
- v3.8
- v3.7-rc8
- v3.7-rc7
- v3.7-rc6
- v3.7-rc5
- v3.7-rc4
- v3.7-rc3
- v3.7-rc2
- v3.7-rc1
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- v3.6-rc6
- v3.6-rc5
- v3.6-rc4
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- v3.6-rc2
- v3.6-rc1
- v3.6
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- v3.5-rc6
- v3.5-rc5
- v3.5-rc4
- v3.5-rc3
- v3.5-rc2
- v3.5-rc1
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- v3.4-rc6
- v3.4-rc5
- v3.4-rc4
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- v3.4-rc2
- v3.4-rc1
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- v3.3-rc5
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- v3.3-rc2
- v3.3-rc1
- v3.3
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- v3.2-rc4
- v3.2-rc3
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- v3.2-rc1
- v3.2
- v3.19-rc7
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- v3.13-rc4
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- v3.0
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- v2.6.39-rc1
- v2.6.39
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- v2.6.38-rc7
- v2.6.38-rc6
- v2.6.38-rc5
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- v2.6.38-rc3
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- v2.6.38-rc1
- v2.6.38
- v2.6.37-rc8
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- v2.6.37-rc3
- v2.6.37-rc2
- v2.6.37-rc1
- v2.6.37
- v2.6.36-rc8
- v2.6.36-rc7
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- v2.6.36-rc5
- v2.6.36-rc4
- v2.6.36-rc3
- v2.6.36-rc2
- v2.6.36-rc1
- v2.6.36
- v2.6.35-rc6
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- v2.6.35
- v2.6.34-rc7
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- v2.6.34
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- v2.6.33
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- v2.6.31-rc3
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- v2.6.31-rc1
- v2.6.31
- v2.6.30-rc8
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- v2.6.30-rc1
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- v2.6.29-rc8
- v2.6.29-rc7
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- v2.6.29
- v2.6.28-rc9
- v2.6.28-rc8
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- v2.6.27-rc9
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- v2.6.27
- v2.6.26-rc9
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- v2.6.26-rc5
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- v2.6.25-rc9
- v2.6.25-rc8
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- v2.6.24
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- v2.6.23
- v2.6.22-rc7
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- v2.6.22
- v2.6.21-rc7
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- v2.6.19
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Tip revision: 40ffbfad6bb79a99cc7627bdaca0ee22dec526f6 authored by Linus Torvalds on 01 September 2007, 06:08:24 UTC
Linux 2.6.23-rc5
Linux 2.6.23-rc5
Tip revision: 40ffbfa
flush.S
/*
* Cache flushing routines.
*
* Copyright (C) 1999-2001, 2005 Hewlett-Packard Co
* David Mosberger-Tang <davidm@hpl.hp.com>
*
* 05/28/05 Zoltan Menyhart Dynamic stride size
*/
#include <asm/asmmacro.h>
/*
* flush_icache_range(start,end)
*
* Make i-cache(s) coherent with d-caches.
*
* Must deal with range from start to end-1 but nothing else (need to
* be careful not to touch addresses that may be unmapped).
*
* Note: "in0" and "in1" are preserved for debugging purposes.
*/
.section .kprobes.text,"ax"
GLOBAL_ENTRY(flush_icache_range)
.prologue
alloc r2=ar.pfs,2,0,0,0
movl r3=ia64_i_cache_stride_shift
mov r21=1
;;
ld8 r20=[r3] // r20: stride shift
sub r22=in1,r0,1 // last byte address
;;
shr.u r23=in0,r20 // start / (stride size)
shr.u r22=r22,r20 // (last byte address) / (stride size)
shl r21=r21,r20 // r21: stride size of the i-cache(s)
;;
sub r8=r22,r23 // number of strides - 1
shl r24=r23,r20 // r24: addresses for "fc.i" =
// "start" rounded down to stride boundary
.save ar.lc,r3
mov r3=ar.lc // save ar.lc
;;
.body
mov ar.lc=r8
;;
/*
* 32 byte aligned loop, even number of (actually 2) bundles
*/
.Loop: fc.i r24 // issuable on M0 only
add r24=r21,r24 // we flush "stride size" bytes per iteration
nop.i 0
br.cloop.sptk.few .Loop
;;
sync.i
;;
srlz.i
;;
mov ar.lc=r3 // restore ar.lc
br.ret.sptk.many rp
END(flush_icache_range)