Revision f08e457cecece7fbbdad3add9defac3373a59b5a authored by Borislav Petkov on 21 March 2011, 19:45:06 UTC, committed by Borislav Petkov on 26 April 2011, 14:18:44 UTC
F15h and later use a portion of DRAM as a CC6 storage area. BIOS programs D18F1x[17C:140,7C:40] DRAM Base/Limit accordingly by subtracting the storage area from the DRAM limit setting. However, in order for edac to consider that part of DRAM too, we need to include it into the per-node range. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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File | Mode | Size |
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Documentation | ||
arch | ||
block | ||
crypto | ||
drivers | ||
firmware | ||
fs | ||
include | ||
init | ||
ipc | ||
kernel | ||
lib | ||
mm | ||
net | ||
samples | ||
scripts | ||
security | ||
sound | ||
tools | ||
usr | ||
virt | ||
.gitignore | -rw-r--r-- | 941 bytes |
.mailmap | -rw-r--r-- | 4.1 KB |
COPYING | -rw-r--r-- | 18.3 KB |
CREDITS | -rw-r--r-- | 91.7 KB |
Kbuild | -rw-r--r-- | 2.4 KB |
Kconfig | -rw-r--r-- | 252 bytes |
MAINTAINERS | -rw-r--r-- | 188.2 KB |
Makefile | -rw-r--r-- | 51.1 KB |
README | -rw-r--r-- | 17.1 KB |
REPORTING-BUGS | -rw-r--r-- | 3.3 KB |
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