Revision 1e6e57d9b34a9075d5f9e2048ea7b09756590d11 authored by Will Deacon on 04 July 2016, 16:44:48 UTC, committed by Will Deacon on 19 October 2016, 14:37:29 UTC
Writing the outer loop of an LL/SC sequence using do {...} while
constructs potentially allows the compiler to hoist memory accesses
between the STXR and the branch back to the LDXR. On CPUs that do not
guarantee forward progress of LL/SC loops when faced with memory
accesses to the same ERG (up to 2k) between the failed STXR and the
branch back, we may end up livelocking.
This patch avoids this issue in our percpu atomics by rewriting the
outer loop as part of the LL/SC inline assembly block.
Cc: <stable@vger.kernel.org>
Fixes: f97fc810798c ("arm64: percpu: Implement this_cpu operations")
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
1 parent 1c5b51d
| File | Mode | Size |
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| 3com | ||
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| adaptec | ||
| advansys | ||
| av7110 | ||
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| cis | ||
| cpia2 | ||
| cxgb3 | ||
| dsp56k | ||
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| ess | ||
| kaweth | ||
| keyspan | ||
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| korg | ||
| matrox | ||
| myricom | ||
| ositech | ||
| qlogic | ||
| r128 | ||
| radeon | ||
| sb16 | ||
| sun | ||
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| vicam | ||
| yam | ||
| yamaha | ||
| .gitignore | -rw-r--r-- | 39 bytes |
| Makefile | -rw-r--r-- | 10.9 KB |
| README.AddingFirmware | -rw-r--r-- | 1.7 KB |
| WHENCE | -rw-r--r-- | 26.3 KB |
| atmsar11.HEX | -rw-r--r-- | 18.7 KB |
| ihex2fw.c | -rw-r--r-- | 6.6 KB |
| mts_cdma.fw.ihex | -rw-r--r-- | 37.2 KB |
| mts_edge.fw.ihex | -rw-r--r-- | 37.8 KB |
| mts_gsm.fw.ihex | -rw-r--r-- | 37.2 KB |
| ti_3410.fw.ihex | -rw-r--r-- | 37.0 KB |
| ti_5052.fw.ihex | -rw-r--r-- | 37.0 KB |
| whiteheat.HEX | -rw-r--r-- | 43.9 KB |
| whiteheat_loader.HEX | -rw-r--r-- | 11.8 KB |
| whiteheat_loader_debug.HEX | -rw-r--r-- | 17.2 KB |
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