Revision 2022c1f136067f673964dcaffa1cae1008ddcd74 authored by Russ Anderson on 03 January 2008, 16:23:49 UTC, committed by Tony Luck on 03 January 2008, 21:22:54 UTC
Montecito and Montvale behaves slightly differently than previous Itanium processors, resulting in the MCA due to a failed PIO read to sometimes surfacing outside the nofault code. This code is based on discussions with Intel CPU architects and verified at customer sites. Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
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