Revision 38b45c87861e5461283609f3aa2df31b141faae6 authored by Guillaume Revaillot on 21 January 2019, 14:36:49 UTC, committed by Karl Palsson on 08 November 2019, 14:19:17 UTC
v2 "single" peripheral with a couple of tweaks : - added registers to configure two additionnal advanced analog watchdog. - different adc sampling time time based on channel groups. - 8 steps adc sequence injection, using chselr/chselrmode. And a note on the rm explaining that after every configuration change to ADC_CFGR1's SCANDIR or CHSELRMOD or CHSELR register, user need to check that configuration is applied before any other modification / adc conversion start.. making adc_set_reqular a bit painfull to read..
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| File | Mode | Size |
|---|---|---|
| data | ||
| checkpatch.pl | -rwxr-xr-x | 101.2 KB |
| gendoxylayout.py | -rwxr-xr-x | 2.3 KB |
| gendoxylist | -rwxr-xr-x | 1.1 KB |
| genlink.py | -rwxr-xr-x | 3.4 KB |
| genlinktest.sh | -rwxr-xr-x | 1.5 KB |
| irq2nvic_h | -rwxr-xr-x | 5.6 KB |
| lpcvtcksum | -rwxr-xr-x | 1.7 KB |
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