Revision 6910ceb5cababfefffc4ddc58a085a71c0ab9f22 authored by Russell King on 18 June 2013, 16:20:32 UTC, committed by Wim Van Sebroeck on 11 July 2013, 20:18:30 UTC
The bits in BRIDGE_CAUSE are documented as RW0C - read, write 0 to clear. If we read the register, mask off the watchdog bit, and write it back, we're actually clearing every interrupt which wasn't pending at the time we read the register - and that is racy. Fix this to only write ~WATCHDOG_BIT to the register, which means we write as zero only the watchdog bit. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Jason Cooper <jason@lakedaemon.net> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
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| File | Mode | Size |
|---|---|---|
| Makefile | -rw-r--r-- | 394 bytes |
| compat.c | -rw-r--r-- | 19.2 KB |
| compat_mq.c | -rw-r--r-- | 4.1 KB |
| ipc_sysctl.c | -rw-r--r-- | 6.9 KB |
| ipcns_notifier.c | -rw-r--r-- | 2.2 KB |
| mq_sysctl.c | -rw-r--r-- | 2.7 KB |
| mqueue.c | -rw-r--r-- | 35.4 KB |
| msg.c | -rw-r--r-- | 23.0 KB |
| msgutil.c | -rw-r--r-- | 3.6 KB |
| namespace.c | -rw-r--r-- | 4.6 KB |
| sem.c | -rw-r--r-- | 52.3 KB |
| shm.c | -rw-r--r-- | 30.4 KB |
| syscall.c | -rw-r--r-- | 2.3 KB |
| util.c | -rw-r--r-- | 22.5 KB |
| util.h | -rw-r--r-- | 5.9 KB |
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