https://github.com/torvalds/linux
Revision 976e78a5226598cb582fe9ef98a72861adbc0e9c authored by Eugeniy Paltsev on 12 September 2017, 18:20:45 UTC, committed by Vineet Gupta on 04 October 2017, 03:36:49 UTC
DW sdio controller has external ciu clock divider controlled
via register in SDIO IP. It divides sdio_ref_clk
(which comes from CGU) by 16 for default. So default mmcclk
clock (which comes to sdk_in) is 25000000 Hz.

So fix wrong current value (50000000 Hz) to actual 25000000 Hz.

Note this is a preventive fix, in line with similar change for HSDK
where this was actually needed. see:
http://lists.infradead.org/pipermail/linux-snps-arc/2017-September/002924.html

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
1 parent 6afa3bc
History
Tip revision: 976e78a5226598cb582fe9ef98a72861adbc0e9c authored by Eugeniy Paltsev on 12 September 2017, 18:20:45 UTC
ARC: [plat-axs10x] sdio: Temporary fix of sdio ciu frequency
Tip revision: 976e78a

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