Revision d45364e6d4b7125c9d2abac6f63eec509316195f authored by Prasad Singamsetty on 14 November 2017, 23:13:49 UTC, committed by Michael Roth on 21 June 2018, 01:45:05 UTC
The current implementation of Intel IOMMU code only supports 39 bits
host/iova address width so number of macros use hard coded values based
on that. This patch is to redefine them so they can be used with
variable address widths. This patch doesn't add any new functionality
but enables adding support for 48 bit address width.

Signed-off-by: Prasad Singamsetty <prasad.singamsety@oracle.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
(cherry picked from commit 92e5d85e8345a22e87eda940ffe0f6422eb45360)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
1 parent 7128bcb
History
File Mode Size
config
devel
interop
specs
spin
COLO-FT.txt -rw-r--r-- 9.9 KB
block-replication.txt -rw-r--r-- 10.2 KB
bootindex.txt -rw-r--r-- 2.4 KB
ccid.txt -rw-r--r-- 7.5 KB
colo-proxy.txt -rw-r--r-- 11.1 KB
generic-loader.txt -rw-r--r-- 4.2 KB
igd-assign.txt -rw-r--r-- 7.1 KB
image-fuzzer.txt -rw-r--r-- 9.4 KB
memory-hotplug.txt -rw-r--r-- 3.3 KB
multi-thread-compression.txt -rw-r--r-- 5.7 KB
multiseat.txt -rw-r--r-- 5.0 KB
nvdimm.txt -rw-r--r-- 4.7 KB
pci_expander_bridge.txt -rw-r--r-- 2.7 KB
pcie.txt -rw-r--r-- 14.4 KB
pcie_pci_bridge.txt -rw-r--r-- 4.4 KB
pr-manager.rst -rw-r--r-- 4.7 KB
qcow2-cache.txt -rw-r--r-- 5.7 KB
qdev-device-use.txt -rw-r--r-- 13.4 KB
qemu-block-drivers.texi -rw-r--r-- 30.0 KB
qemu_logo.pdf -rw-r--r-- 8.9 KB
qemupciserial.inf -rw-r--r-- 2.9 KB
rdma.txt -rw-r--r-- 18.0 KB
replay.txt -rw-r--r-- 11.1 KB
spice-port-fqdn.txt -rw-r--r-- 490 bytes
throttle.txt -rw-r--r-- 10.3 KB
usb-storage.txt -rw-r--r-- 2.5 KB
usb2.txt -rw-r--r-- 5.8 KB
virtio-balloon-stats.txt -rw-r--r-- 3.5 KB
xbzrle.txt -rw-r--r-- 4.8 KB
xen-save-devices-state.txt -rw-r--r-- 1000 bytes

back to top