Revision d4f513ff12c1d74b379715e78c01002f5d055315 authored by Vipul Kumar Samar on 06 July 2012, 10:22:36 UTC, committed by Shiraz Hashim on 18 July 2012, 04:34:53 UTC
sys_clk has multiple parents and selection of parent depends on sys_clk_ctrl register bit no. 23:25, with following possibilities 0XX: pll1_clk 10X: sys_synth_clk 110: pll2_clk 111: pll3_clk Out of several possibilities (h/w wise) to select same clock parent for sys_clk, current clock implementation was considering just one value. When bootloader programmed different (valid) value to select a clock parent then Linux breaks. Here, we try to include all possibilities which can lead to same clock selection thus making Linux independent of bootloader selection values. Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
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3com | ||
acenic | ||
adaptec | ||
advansys | ||
av7110 | ||
bnx2 | ||
bnx2x | ||
cis | ||
cpia2 | ||
cxgb3 | ||
dabusb | ||
dsp56k | ||
e100 | ||
edgeport | ||
emi26 | ||
emi62 | ||
ess | ||
kaweth | ||
keyspan | ||
keyspan_pda | ||
korg | ||
matrox | ||
myricom | ||
ositech | ||
qlogic | ||
r128 | ||
radeon | ||
sb16 | ||
sun | ||
tehuti | ||
tigon | ||
ttusb-budget | ||
vicam | ||
yam | ||
yamaha | ||
.gitignore | -rw-r--r-- | 39 bytes |
Makefile | -rw-r--r-- | 11.6 KB |
README.AddingFirmware | -rw-r--r-- | 1.5 KB |
WHENCE | -rw-r--r-- | 26.5 KB |
atmsar11.HEX | -rw-r--r-- | 18.7 KB |
ihex2fw.c | -rw-r--r-- | 6.6 KB |
intelliport2.bin.ihex | -rw-r--r-- | 92.2 KB |
mts_cdma.fw.ihex | -rw-r--r-- | 37.2 KB |
mts_edge.fw.ihex | -rw-r--r-- | 37.8 KB |
mts_gsm.fw.ihex | -rw-r--r-- | 37.2 KB |
ti_3410.fw.ihex | -rw-r--r-- | 37.0 KB |
ti_5052.fw.ihex | -rw-r--r-- | 37.0 KB |
whiteheat.HEX | -rw-r--r-- | 43.9 KB |
whiteheat_loader.HEX | -rw-r--r-- | 11.8 KB |
whiteheat_loader_debug.HEX | -rw-r--r-- | 17.2 KB |
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