Revision d4f513ff12c1d74b379715e78c01002f5d055315 authored by Vipul Kumar Samar on 06 July 2012, 10:22:36 UTC, committed by Shiraz Hashim on 18 July 2012, 04:34:53 UTC
sys_clk has multiple parents and selection of parent depends on sys_clk_ctrl register bit no. 23:25, with following possibilities 0XX: pll1_clk 10X: sys_synth_clk 110: pll2_clk 111: pll3_clk Out of several possibilities (h/w wise) to select same clock parent for sys_clk, current clock implementation was considering just one value. When bootloader programmed different (valid) value to select a clock parent then Linux breaks. Here, we try to include all possibilities which can lead to same clock selection thus making Linux independent of bootloader selection values. Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
1 parent d9ba8db
| File | Mode | Size |
|---|---|---|
| .gitignore | -rw-r--r-- | 6 bytes |
| 3CCFEM556.cis.ihex | -rw-r--r-- | 469 bytes |
| 3CXEM556.cis.ihex | -rw-r--r-- | 463 bytes |
| COMpad2.cis.ihex | -rw-r--r-- | 363 bytes |
| COMpad4.cis.ihex | -rw-r--r-- | 276 bytes |
| DP83903.cis.ihex | -rw-r--r-- | 499 bytes |
| LA-PCM.cis.ihex | -rw-r--r-- | 758 bytes |
| MT5634ZLX.cis.ihex | -rw-r--r-- | 363 bytes |
| NE2K.cis.ihex | -rw-r--r-- | 233 bytes |
| PCMLM28.cis.ihex | -rw-r--r-- | 662 bytes |
| PE-200.cis.ihex | -rw-r--r-- | 255 bytes |
| PE520.cis.ihex | -rw-r--r-- | 266 bytes |
| RS-COM-2P.cis.ihex | -rw-r--r-- | 307 bytes |
| SW_555_SER.cis.ihex | -rw-r--r-- | 412 bytes |
| SW_7xx_SER.cis.ihex | -rw-r--r-- | 460 bytes |
| SW_8xx_SER.cis.ihex | -rw-r--r-- | 444 bytes |
| tamarack.cis.ihex | -rw-r--r-- | 311 bytes |
Computing file changes ...
