Revision d57019d1858a6f9b3ca05d76d793466ae428cfa3 authored by Sergei Shtylyov on 22 March 2016, 21:44:40 UTC, committed by David S. Miller on 23 March 2016, 17:38:40 UTC
The driver of course "knows" that the chip's reset signal is active low,
so  it drives the GPIO to 0  to reset the PHY and to 1 otherwise; however
all this will only work iff the GPIO  is  specified as active-high in the
device tree!  I think both the driver and the device trees (if there are
any -- I was unable to find them) need to be fixed in this case...

Fixes: 13a56b449325 ("net: phy: at803x: Add support for hardware reset")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
1 parent 9a34921
History
File Mode Size
Kconfig -rw-r--r-- 442 bytes
Makefile -rw-r--r-- 251 bytes
attr.c -rw-r--r-- 2.6 KB
bfind.c -rw-r--r-- 4.5 KB
bitmap.c -rw-r--r-- 5.8 KB
bnode.c -rw-r--r-- 11.3 KB
brec.c -rw-r--r-- 13.5 KB
btree.c -rw-r--r-- 8.7 KB
btree.h -rw-r--r-- 5.1 KB
catalog.c -rw-r--r-- 9.2 KB
dir.c -rw-r--r-- 7.6 KB
extent.c -rw-r--r-- 13.8 KB
hfs.h -rw-r--r-- 9.1 KB
hfs_fs.h -rw-r--r-- 8.9 KB
inode.c -rw-r--r-- 18.3 KB
mdb.c -rw-r--r-- 10.1 KB
part_tbl.c -rw-r--r-- 2.9 KB
string.c -rw-r--r-- 3.7 KB
super.c -rw-r--r-- 12.2 KB
sysdep.c -rw-r--r-- 1.0 KB
trans.c -rw-r--r-- 3.4 KB

back to top