Revision da30e0ac0f9a521f0cfec8145ddd1ad131f66d61 authored by Catalin Marinas on 07 December 2010, 15:56:29 UTC, committed by Russell King on 12 December 2010, 23:25:58 UTC
The current implementation of the v7_coherent_*_range function assumes that the D and I cache lines have the same size, which is incorrect architecturally. This patch adds the icache_line_size macro which reads the CTR register. The main loop in v7_coherent_*_range is split in two independent loops or the D and I caches. This also has the performance advantage that the DSB is moved outside the main loop. Reported-by: Kevin Sapp <ksapp@quicinc.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1 parent f91e2c3
File | Mode | Size |
---|---|---|
Documentation | ||
arch | ||
block | ||
crypto | ||
drivers | ||
firmware | ||
fs | ||
include | ||
init | ||
ipc | ||
kernel | ||
lib | ||
mm | ||
net | ||
samples | ||
scripts | ||
security | ||
sound | ||
tools | ||
usr | ||
virt | ||
.gitignore | -rw-r--r-- | 936 bytes |
.mailmap | -rw-r--r-- | 3.9 KB |
COPYING | -rw-r--r-- | 18.3 KB |
CREDITS | -rw-r--r-- | 91.8 KB |
Kbuild | -rw-r--r-- | 2.4 KB |
Kconfig | -rw-r--r-- | 252 bytes |
MAINTAINERS | -rw-r--r-- | 178.4 KB |
Makefile | -rw-r--r-- | 50.9 KB |
README | -rw-r--r-- | 17.1 KB |
REPORTING-BUGS | -rw-r--r-- | 3.3 KB |
![swh spinner](/static/img/swh-spinner.gif)
Computing file changes ...