Revision da30e0ac0f9a521f0cfec8145ddd1ad131f66d61 authored by Catalin Marinas on 07 December 2010, 15:56:29 UTC, committed by Russell King on 12 December 2010, 23:25:58 UTC
The current implementation of the v7_coherent_*_range function assumes that the D and I cache lines have the same size, which is incorrect architecturally. This patch adds the icache_line_size macro which reads the CTR register. The main loop in v7_coherent_*_range is split in two independent loops or the D and I caches. This also has the performance advantage that the DSB is moved outside the main loop. Reported-by: Kevin Sapp <ksapp@quicinc.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1 parent f91e2c3
| File | Mode | Size |
|---|---|---|
| Kconfig | -rw-r--r-- | 40.8 KB |
| Makefile | -rw-r--r-- | 1.0 KB |
| calibrate.c | -rw-r--r-- | 5.1 KB |
| do_mounts.c | -rw-r--r-- | 10.9 KB |
| do_mounts.h | -rw-r--r-- | 1.4 KB |
| do_mounts_initrd.c | -rw-r--r-- | 3.1 KB |
| do_mounts_md.c | -rw-r--r-- | 7.9 KB |
| do_mounts_rd.c | -rw-r--r-- | 8.1 KB |
| initramfs.c | -rw-r--r-- | 12.6 KB |
| main.c | -rw-r--r-- | 21.6 KB |
| noinitramfs.c | -rw-r--r-- | 1.5 KB |
| version.c | -rw-r--r-- | 1.1 KB |
Computing file changes ...
