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Tip revision: a8fa8f03b50a72034009439908f1339f4ce94518 authored by Ron Burkey on 06 June 2021, 12:28:21 UTC
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ElectroMechanical.html
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<title>Virtual AGC Electrical/Mechanical Page</title>
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<meta name="Author" content="Ronald Burkey">
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<h1><a name="Contents"></a>Contents</h1>
<ul>
<li><a href="#Introduction">Introduction</a></li>
<li><a href="#Accessing_the_Available_GN_Engineering">Accessing
the Available Apollo G&N System Engineering Drawings</a></li>
<ul>
<li><a href="#Search_by_Drawing_Number_or_Title_">Search by
Drawing Number or Title</a></li>
<li><a href="#Browse_by_Drawing_Number">Browse by Drawing Number</a></li>
<li><a href="#Navigate_the_Assembly_Hierarchy_">Navigate the
Mission Assembly Hierarchy</a><br>
</li>
</ul>
<li><a href="#LEM_Engineering_Drawings">LEM Engineering Drawings</a><br>
</li>
<li><a href="#Additional_Engineering_Drawings">Additional
Engineering Drawings</a><br>
</li>
<li><a href="#References">References</a></li>
<li><a href="#Further_Information_About_Scanned">Further
Information About Scanned Engineering Drawings</a><br>
</li>
<li><a href="#Versioning">Versioning the AGC and DSKY<br>
</a></li>
<li><a href="#CAD_Files_and_Images">CAD Transcriptions of Apollo
Engineering Drawings<br>
</a></li>
<ul>
<li><a href="#Electrical_Drawings_">Electrical Drawings</a></li>
<li><a href="#Mechanical_Drawings">Mechanical Drawings</a></li>
</ul>
<ul>
<ul>
<li><a href="#2D_CAD_">2D CAD</a></li>
<li><a href="#3D_Models">3D Models</a></li>
<li><a href="#Submissions">Submissions</a><br>
</li>
</ul>
</ul>
<li><a href="#Digital_Simulation_of_the_AGC_Electronic">Digital
Simulation of the AGC Electronics</a><br>
</li>
<li><a href="#Basic_Partitioning_of_the_AGC">Basic Partitioning of
the AGC Electronics</a><br>
</li>
<li><a href="#Drawings_for_Block_I_AGC">Supplemental Information
for the Block I AGC</a><br>
</li>
<li><a href="#Drawings_for_Block_I_Main_DSKY">Supplemental
Information for the Block I Main and Navigation DSKY</a></li>
<li><a href="#2003100-021">Supplemental Information for LM/Block
II AGC p/n 2003100</a><br>
</li>
<li><a href="#Supplemental2003200">Supplemental Information for
LM/Block II AGC p/n 2003200</a></li>
<li><a href="#2003993-111">Supplemental Information for LM/Block
II AGC p/n 2003993</a></li>
<ul>
</ul>
<li><a href="#Supplemental_Information_for_Block">Supplemental
Information for Block II DSKY</a></li>
<li><a href="#PartNumbers">Appendix: Evolution of Block II AGC
Part Numbers</a><br>
</li>
<li><a href="#Electronics_Component_Part_Numbers">Appendix:
Electronics Component Part Numbers and Their SCDs<br>
</a></li>
<li><a href="#Appendix:_Signal_Wiring_Diagrams">Appendix: Signal
Wiring Diagrams for the Block II and the NOR-Gate Problem</a></li>
<li><a href="#Appendix:_Signal_Wiring_Diagrams_for_the">Appendix:
Signal Wiring Diagrams and the Block I AGC</a></li>
<li><a href="#Appendix:_Software">Appendix: Auxiliary Software</a><br>
</li>
</ul>
<h1><a name="Introduction"></a>Introduction<br>
</h1>
<p>This page is devoted to the electrical and mechanical aspects of
the AGC and DSKY, and more broadly, to the electrical and
mechanical aspects of the entire Apollo CM and LM G&N
(guidance and navigation) system.<br>
</p>
<p>This is an ongoing effort. The long-range goal — or perhaps
"wish" is a more-accurate term — is to provide the following
engineering resources:<br>
</p>
<ol>
<li>The complete set of engineering drawings (electrical
schematics and mechanical drawings) for AGC/DSKY and other
G&N components, in all revisions, in the form of scanned
images of the original Apollo Program drawings.</li>
<li>Contemporary Apollo Program theory-of-operation documents for
the above.<br>
</li>
<li>Electrically and visually accurate transcriptions of those
electrical schematics into a modern open-source electrical CAD
program.</li>
<li>Accurate translation of mechanical drawings of fabricated
parts into reusable 3D models.<br>
</li>
<li>Translation of AGC electrical design into Verilog
hardware-description language or other standardized languages
when appropriate.<br>
</li>
<li>Simulation of the AGC hardware, via modern open-source
Verilog-simulation software, or other software when appropriate.<br>
</li>
</ol>
<p>Great strides have been made toward the goal, but it nevertheless
remains very distant. The far horizons grow no closer.<br>
</p>
<h1><a name="Accessing_the_Available_GN_Engineering"></a>Accessing
the Available G&N Engineering Drawings</h1>
<p>There are three methods, covered in the three sections below.<br>
</p>
<h2><a name="Search_by_Drawing_Number_or_Title_"></a>Search by
Drawing Number or Title</h2>
<table cellspacing="2" cellpadding="2" align="center">
<tbody>
<tr>
<td valign="middle"><font size="+3"><span style="font-family:
sans-serif; font-size: 32px; font-style: normal;
font-variant-ligatures: normal; font-variant-caps:
normal; font-weight: 400; letter-spacing: normal;
text-align: start; text-indent: 0px; text-transform:
none; white-space: normal; word-spacing: 0px;
-webkit-text-stroke-width: 0px; text-decoration-style:
initial; text-decoration-color: initial; display: inline
! important; float: none;">
<meta http-equiv="content-type" content="text/html;
charset=UTF-8">
⇨</span></font></td>
<td valign="middle"><span style="font-family: sans-serif;
font-size: 32px; font-style: normal;
font-variant-ligatures: normal; font-variant-caps: normal;
font-weight: 400; letter-spacing: normal; text-align:
start; text-indent: 0px; text-transform: none;
white-space: normal; word-spacing: 0px;
-webkit-text-stroke-width: 0px; text-decoration-style:
initial; text-decoration-color: initial; display: inline !
important; float: none;"></span><a href="TipueSearch.html">Go
to the Apollo G&N engineering-drawing title
search-engine page</a></td>
</tr>
</tbody>
</table>
<h2><a name="Browse_by_Drawing_Number"></a><a
name="Browse_the_Numerically-Ordered_List_of_"></a>Browse by
Drawing Number<br>
</h2>
To find any given drawing by its drawing number, first look in the
"box" that covers that drawing-number range. Then consult the
"miscellaneous" drawings if what you want is missing from the box or
is illegible, or is simply too early a revision. The
exceptions are mil specs (drawings with numbers like MS<i>xxxx</i>
or NAS<i>xxxx</i>), since if we have them they'll always appear on
the dedicated MIL-SPEC page rather than being mixed in with the
other drawings. I should point out some drawings appear in the
wrong boxes, numerically, for several possible reasons, though
perhaps 99.9% of the drawings are numerically in the correct boxes.<br>
<blockquote>
<table cellspacing="2" cellpadding="2" border="1" align="center">
<tbody>
<tr>
<td valign="top"><a href="AgcDrawingIndexBox431.html">Box
431</a>, 102010-1000275<span style="color: rgb(0, 0, 0); font-family: Arial; font-size: 13px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: right; text-indent: 0px; text-transform: none; white-space: pre-wrap; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: rgb(255, 255, 255); text-decoration-style: initial; text-decoration-color: initial; display: inline !important; float: none;"></span>
</td>
<td valign="top"><a href="AgcDrawingIndexBox432.html">Box
432</a>, 1000283-1002237<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox433.html">Box
433</a>, 1002240-1002323<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox434.html">Box
434</a>, 1002323-1002325<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox435.html">Box
435</a>, 1002325-1002349<br>
</td>
</tr>
<tr>
<td valign="top"><a href="AgcDrawingIndexBox436.html">Box
436</a>, 1002349-1003081<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox437.html">Box
437</a>, 1003082-1003733<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox438.html">Box
438</a>, 1003733-1005799<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox439.html">Box
439</a>, 1006002-1006898<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox440.html">Box
440</a>, 1006904-1007131<br>
</td>
</tr>
<tr>
<td valign="top"><a href="AgcDrawingIndexBox441.html">Box
441</a>, 1007141-1007547<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox442.html">Box
442</a>, 1007548-1008271<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox443.html">Box
443</a>, 1008283-1010253<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox444.html">Box
444</a>, 1010254-1010493<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox445.html">Box
445</a>, 1010494-1011399<br>
</td>
</tr>
<tr>
<td valign="top"><a href="AgcDrawingIndexBox446.html">Box
446</a>, 1011400-1014219<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox447.html">Box
447</a>, 1014221-1014999<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox448.html">Box
448</a>, 1015000-1015739<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox449.html">Box
449</a>, 1015740-1016118<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox450.html">Box
450</a>, 1016122-1019690<br>
</td>
</tr>
<tr>
<td valign="top"><a href="AgcDrawingIndexBox451.html">Box
451</a>, 1019691-1021200<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox452.html">Box
452</a>, 1021200-1897187<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox453.html">Box
453</a>, 1897190-1900098<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox454.html">Box
454</a>, 1900100-1900712<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox455.html">Box
455</a>, 1900713-1900943<br>
</td>
</tr>
<tr>
<td valign="top"><a href="AgcDrawingIndexBox456.html">Box
456</a>, 1900943-1901695<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox457.html">Box
457</a>, 1901700-1902397<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox458.html">Box
458</a>, 1902404-2003120<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox459.html">Box
459</a>, 2003121-2005061 </td>
<td valign="top"><a href="AgcDrawingIndexBox460.html">Box
460</a>, 2005062-2007114<br>
</td>
</tr>
<tr>
<td valign="top"><a href="AgcDrawingIndexBox461.html">Box
461</a>, 2007115-2007239 </td>
<td valign="top"><a href="AgcDrawingIndexBox462.html">Box
462</a>, 2007240-2010084 <br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox463.html">Box
463</a>, 2010085-2012508 <br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox464.html">Box
464</a>, 2012509-2014643<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox465.html">Box
465</a>, 2014644-2015500<br>
</td>
</tr>
<tr>
<td valign="top"><a href="AgcDrawingIndexBox466.html">Box
466</a>, 2015502-2018632<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox467.html">Box
467</a>, 2018634-2021670<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox468.html">Box
468</a>, 2021971-2900541<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox469.html">Box
469</a>, 2900542-2901129<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox470.html">Box
470</a>, 2901143-6010677<br>
</td>
</tr>
<tr>
<td valign="top"><a href="AgcDrawingIndexBox471.html">Box
471</a>, 6010678-6015000<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox472.html">Box
472</a>, 6015000-8106098<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox473.html">Box
473</a>, JDC0001-JDC04390<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox474.html">Box
474</a>, JDC4409-JDC10709<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox475.html">Box
475</a>, JDC10710-JDC12621<br>
</td>
</tr>
<tr>
<td valign="top"><a href="AgcDrawingIndexBox476.html">Box
476</a>, JDC12622-JDC18874<br>
</td>
<td valign="top"><a href="AgcDrawingIndexBox477.html">Box
477</a>, JDC19021-MC25922<br>
</td>
<td valign="top"><br>
</td>
<td valign="top"><a href="AgcDrawingIndexMilSpec.html">Mil-Spec
drawings</a><br>
</td>
<td valign="top"><a href="AgcDrawingIndex.html">Miscellaneous
drawings</a><br>
</td>
</tr>
</tbody>
</table>
</blockquote>
<h2><a name="Navigate_the_Assembly_Hierarchy_"></a><a
name="Browse_the_Available_Engineering"></a>Navigate the Mission
Assembly Hierarchy<br>
</h2>
<h1> </h1>
<p> </p>
In this section, the engineering drawings for the onboard Guidance
& Navigation (G&N) systems in the Command Module and Lunar
Module are provided on a mission-by-mission basis. Note,
though, that there are assemblies in the engineering-drawing set
that don't form any part of the spacecraft's onboard G&N system,
and those assemblies aren't covered in this section; an example
would be the AGC's test set.<br>
<br>
Each mission had either one or two G&N systems installed:
one for the CM and for the LM, but of course not every mission had
an LM. Each G&N system is identified by a numerical
assembly number (<a
href="https://archive.org/stream/AgcApertureCardsBatch10Images#page/n234/mode/2up">1014999</a>
for Block I CM, <a
href="https://archive.org/stream/AgcApertureCardsBatch4Images#page/n197/mode/2up">2014999</a>
for Block II CM, <a
href="https://archive.org/stream/AgcApertureCardsBatch20190219Images#page/n79/mode/1uphttps://archive.org/stream/AgcApertureCardsBatch20190219Images#page/n79/mode/1up">6014999</a>
for LM) plus a 3-digit configuration number (-000, -021, -031, ... ,
-221) that changed from one mission to the next. For example,
the Apollo 11 LM had G&N system 6014999-091. Note, by the
way, that we're presenting these assemblies entirely from a NASA
perspective; changes were made to the G&N system configurations
<i>after</i> MIT/IL delivered them to NASA, and there's a completely
different set of drawings (1015000, 2015000, 6015000) that describe
the G&N system configurations at the time they were shipped to
NASA. MIT/IL's configuration documentation is naturally similar to
NASA's but doesn't reflect the updates to the systems made after
NASA had received them.<br>
<br>
Such a G&N system is represented by a set of engineering
drawings. Given the top-level drawings of the G&N system, you
can then look at the drawings of any of its sub-assemblies (AGC,
DSKY, CDU, etc.), any of the drawings of the sub-assemblies of the
sub-assemblies, and so on. I call this hierarchy of the
G&N system and its various subassemblies an "assembly
drilldown". <br>
<br>
<table cellspacing="2" cellpadding="2" border="1" align="center">
<tbody>
<tr>
<th valign="bottom" nowrap="nowrap" align="center">G&N
System<br>
Part Number<br>
</th>
<th valign="bottom" nowrap="nowrap" align="left">G&N
System Serial Number<br>
(Spacecraft, Mission)<br>
</th>
</tr>
<tr align="center">
<td colspan="6" valign="top"><i>Block I CM Systems</i><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="1014999-000.html">1014999-000</a><br>
</td>
<td valign="middle" nowrap="nowrap">5<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="1014999-011.html">1014999-011</a><br>
</td>
<td valign="middle" nowrap="nowrap">6<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="1014999-021.html">1014999-021</a><br>
</td>
<td valign="middle" nowrap="nowrap">7<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="1014999-031.html">1014999-031</a><br>
</td>
<td valign="middle" nowrap="nowrap">8<br>
</td>
</tr>
<tr>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="1014999-041.html">1014999-041</a></td>
<td valign="middle" nowrap="nowrap">12<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="1014999-051.html">1014999-051</a><br>
</td>
<td valign="middle" nowrap="nowrap">17 (CSM-011, AS-202,
"Apollo 3")<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="1014999-061.html">1014999-061</a></td>
<td valign="middle" nowrap="nowrap">20 </td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="1014999-071.html">1014999-071</a></td>
<td valign="middle" nowrap="nowrap">109<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="1014999-081.html">1014999-081</a></td>
<td valign="middle" nowrap="nowrap">110 (Qualification system)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="1014999-091.html">1014999-091</a></td>
<td valign="middle" nowrap="nowrap">111 (Qualification system)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="1014999-101.html">1014999-101</a></td>
<td valign="middle" nowrap="nowrap">121<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="1014999-111.html">1014999-111</a></td>
<td valign="middle" nowrap="nowrap">122 (CMO-17, Apollo 4)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="1014999-121.html">1014999-121</a></td>
<td valign="middle" nowrap="nowrap">123 (CMO-20, Apollo 6)<br>
</td>
</tr>
<tr align="center">
<td colspan="6" valign="top"><i>Block II CM Systems</i></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-011.html">2014999-011</a><br>
</td>
<td valign="middle" nowrap="nowrap">201<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-021.html">2014999-021</a></td>
<td valign="middle" nowrap="nowrap">202 (CSM-098, 2TV-1)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-041.html">2014999-041</a></td>
<td valign="middle" nowrap="nowrap">204 (CSM-101, Apollo 7)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-051.html">2014999-051</a></td>
<td valign="middle" nowrap="nowrap">205 (CSM-116, Skylab 2)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-061.html">2014999-061</a></td>
<td valign="middle" nowrap="nowrap">206 (CSM-106, Apollo 10)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-071.html">2014999-071</a></td>
<td valign="middle" nowrap="nowrap">207 <br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-081.html">2014999-081</a></td>
<td valign="middle" nowrap="nowrap">208 (CSM-103, Apollo 8)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-091.html">2014999-091</a></td>
<td valign="middle" nowrap="nowrap">209 (CSM-104, Apollo 9)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-101.html">2014999-101</a></td>
<td valign="middle" nowrap="nowrap">210 (CSM-107, Apollo 11)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-111.html">2014999-111</a></td>
<td valign="middle" nowrap="nowrap">211 (CSM-108, Apollo 12)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-121.html">2014999-121</a></td>
<td valign="middle" nowrap="nowrap">212 (CSM-109, Apollo 13)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-131.html">2014999-131</a></td>
<td valign="middle" nowrap="nowrap">213 (CSM-119, Skylab,
Rescue / ASTP Backup)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-141.html">2014999-141</a></td>
<td valign="middle" nowrap="nowrap">214 (CSM-110, Apollo 14)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-151.html">2014999-151</a></td>
<td valign="middle" nowrap="nowrap">215 (CSM-111, ASTP)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-161.html">2014999-161</a></td>
<td valign="middle" nowrap="nowrap">216 (CSM-113, Apollo 16)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-171.html">2014999-171</a></td>
<td valign="middle" nowrap="nowrap">217 (CSM-112, Apollo 15)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-181.html">2014999-181</a></td>
<td valign="middle" nowrap="nowrap">218 (CSM-114, Apollo 17)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-191.html">2014999-191</a></td>
<td valign="middle" nowrap="nowrap">219 (CSM-115)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-201.html">2014999-201</a></td>
<td valign="middle" nowrap="nowrap">220 (CSM-115A)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-211.html">2014999-211</a></td>
<td valign="middle" nowrap="nowrap">221 (CSM-117, Skylab 3)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="2014999-221.html">2014999-221</a></td>
<td valign="middle" nowrap="nowrap">222 (CSM-118, Skylab 4)<br>
</td>
</tr>
<tr align="center">
<td colspan="6" valign="top"><i>LM Systems</i><br>
</td>
</tr>
<tr>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="6014999-021.html">6014999-021</a></td>
<td valign="middle" nowrap="nowrap">602 (LTA-8)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="6014999-031.html">6014999-031</a></td>
<td valign="middle" nowrap="nowrap">603 (LM-1, Apollo 5)<br>
</td>
</tr>
<tr>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="6014999-051.html">6014999-051</a></td>
<td valign="middle" nowrap="nowrap">605 (LM-3, Apollo 9)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="6014999-061.html">6014999-061</a></td>
<td valign="middle" nowrap="nowrap">606 (LM-4, Apollo 10)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="6014999-071.html">6014999-071</a></td>
<td valign="middle" nowrap="nowrap">607 (LM-6, Apollo 12)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="6014999-081.html">6014999-081</a><br>
</td>
<td valign="middle" nowrap="nowrap">608 (LM-2)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="6014999-091.html">6014999-091</a></td>
<td valign="middle" nowrap="nowrap">609 (LM-5, Apollo 11)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="6014999-101.html">6014999-101</a></td>
<td valign="middle" nowrap="nowrap">610 (LM-7, Apollo 13)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="6014999-111.html">6014999-111</a></td>
<td valign="middle" nowrap="nowrap">611 (LM-8, Apollo 14)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="6014999-121.html">6014999-121</a></td>
<td valign="middle" nowrap="nowrap">612 (LM-15)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="6014999-131.html">6014999-131</a></td>
<td valign="middle" nowrap="nowrap">613 (LM-9)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="6014999-141.html">6014999-141</a></td>
<td valign="middle" nowrap="nowrap">614 (LM-10, Apollo 15)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="6014999-151.html">6014999-151</a></td>
<td valign="middle" nowrap="nowrap">615 (LM-11, Apollo 16)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="6014999-161.html">6014999-161</a></td>
<td valign="middle" nowrap="nowrap">616 (LM-12, Apollo 17)<br>
</td>
</tr>
<tr>
<td valign="middle" align="center"><a href="6014999-171.html">6014999-171</a></td>
<td valign="middle">617 (LM-13)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap" align="center"><a
href="6014999-181.html">6014999-181</a></td>
<td valign="middle" nowrap="nowrap">618 (LM-14)<br>
</td>
</tr>
<tr align="center">
</tr>
<tr>
</tr>
</tbody>
</table>
<br>
Note that the webpages for the individual G&N configurations
linked above are generated in an automated way which additionally
outputs a JSON representation of the hierarchical assembly
data. The JSON files are not provided on this website, but you
can use the software to generate them for yourself, or to generate
JSON for other assemblies (such as an AGC or a DSKY by
itself). This is significant because it means that you can
load this JSON into a program, perhaps written JavaScript or Python,
and manipulate the assembly-hierarchy data programmatically.
That would allow you to do things like compute total parts counts,
perform failure-rate analyses, and so forth ... if you have any need
whatever to do so! To generate such a JSON file, you will need
to locally clone <a
href="https://github.com/virtualagc/virtualagc/tree/schematics">the
"schematics" branch of our GitHub software repository</a>.
You will also need to have Python 3 installed. You generate
the JSON for a given <tt><i>ASSEMBLY</i></tt> from a command line
by changing into the DrawingTree/ folder and running the command<br>
<blockquote><tt>drilldown.py <i>ASSEMBLY</i> ></tt><tt><i>OUTPUT</i></tt><tt>.html</tt><br>
</blockquote>
The <tt><i>ASSEMBLY</i></tt> name consists of a drawing number to
which a configuration number is suffixed. The only allowed
drawing numbers come from the names of the files
DrawingTree/*.csv. The only allowed configuration numbers come
from the "columns" of the .csv file (if you were, for example, to
load it into a spreadsheet program). For example, the file
2003200L.csv supports configuration numbers -011, -021, -031, -041,
and -051, so you could generate JSON files for assemblies
2003200-011 through 2003200-051. You are unlikely to want the
output HTML file, and thus can discard it. The JSON is always
output with the filename drilldown-<i>ASSEMBLY</i>.json.<br>
<br>
Additionally, the program drilldownCompare.py is provided. It
can make comparisons of two assemblies for which JSON has already
been generated. For example, to compare the guidance systems
for the Apollo 11 and Apollo 12 LM, you would first generate their
JSON<br>
<blockquote><tt>drilldown.py 6014999-091 >temp1.html</tt><tt><br>
</tt><tt>drilldown.py 6014999-071 >temp2.html</tt><br>
</blockquote>
and could then use the command<br>
<blockquote><tt>drilldownCompare.py 6014999-091 6014999-071</tt><br>
</blockquote>
You would find a number of differences in doing so, but perhaps the
one that interested you most might be that assembly 2003993-031 (the
AGC) had changed to 2003993-051. If you now wish to compare
those two AGC assemblies, recall that you need to generate the JSON
for them ... which is easy, but is a hassle. However, the data
for assemblies 2003993-031 and -051 is already contained within the
existing JSON for 6014999-091 and -071, respectively, so
drilldownCompare.py lets you take a bit of a shortcut:<br>
<blockquote><tt>drilldownCompare.py 6014999-091 6014999-071 </tt><tt>2003993-031
2003993-051<br>
</tt></blockquote>
In doing this, you would find out that subassembly 2003983-021 had
changed to 2003983-041, etc. The general syntax is<br>
<blockquote><tt>drilldownCompare.py <i>ASSEMBLY1 ASSEMBLY2</i> [<i>SUBASSEMBLY1
SUBASSEMBLY2</i>]<br>
</tt></blockquote>
<div align="left"><b>Note:</b> The rather complete assembly
drill-down and the software tools described above were preceded by
a set of manually-crafted partial drilldowns of just the AGC and
DSKY, and of just their "major" assemblies and components.
The last time at which those manual drilldowns were available on
the website was at <a
href="https://github.com/virtualagc/virtualagc/tree/4d29078e68a6b423c719512118a1d1815947667a">this
commit of the software repository</a>. It is still
possible to view the manual drilldowns, but to do so you should
should clone the repository (at the commit linked above) onto your
local system and browse ElectroMechanical.html locally.<br>
<h1><a name="LEM_Engineering_Drawings"></a>LEM Engineering
Drawings</h1>
<p>A digression ....<br>
</p>
<p>Though not strictly related to the Apollo on-board computer
systems, nor to the larger topic of the Apollo Guidance &
Navigation System, the Virtual AGC Project is also making an
ongoing effort to scan all available Lunar Module engineering
drawings. These drawings, by Grumman Aircraft Engineering
Corporation (GAEC) and its suppliers, almost always use the
older acronym LEM (Lunar Excursion Module) rather than the newer
abbreviation LM ... and since I like "LEM" better than "LM"
myself, I'll use it whenever I'm talking about the LEM
engineering drawings.<br>
</p>
<p>At present, the LEM drawings are taken mostly from National
Archives and Records Administration Southwest aperture-card
(i.e., microfilm) boxes. There are about 300 boxes of such
drawings, nominally containing 1900 microfilm slides each, so
there over half a million LEM engineering images! If you
scroll down a bit, you'll find a huge table providing index
pages for each of the individual LEM aperture-card boxes ...
i.e., about 300 index pages, each providing lists of drawing
numbers, drawing titles, and links for around 1900 scans.<br>
</p>
<p>But before that, even though it goes without saying, I'd
comment that it would be tough to just wade into these hundreds
of thousands of drawings without knowing where to start.
Therefore, it's useful to know that the <i>top-level</i>
drawings for different generations of the LEM or LTA are:<br>
</p>
<ul>
<li><a href="LemDrawingIndexBox515.html#LTA-1">LDW280-21000
(LTA-1, Box 515)</a></li>
<li><a href="LemDrawingIndexBox515.html#LTA-2">LDW280-22000
(LTA-2, LTA-2R, LTA-10R, Box 515)</a>. LTA-2R flown on
Apollo 6. LTA-10R flown on Apollo 4.<br>
</li>
<li><a href="LemDrawingIndexBox515.html#LTA-3">LDW280-23000
(LTA-3, Box 515)</a></li>
<li><a href="LemDrawingIndexBox517.html#LTA-5">LDW280-25000
(LTA-5, Box 517)</a><br>
</li>
<li><a href="LemDrawingIndexBox518.html#LTA8_TOP_LEVEL_ASSY">LDW280-28000
(LTA-8, Box 518)</a>. Used for thermal-vacuum tests.<a
href="LemDrawingIndexBox518.html#LTA8_TOP_LEVEL_ASSY"><br>
</a></li>
<li><a href="LemDrawingIndexBox521.html#LM-1">LDW280-51000
(LM-1, Box 521)</a>. Flown on Apollo 5.<a
href="LemDrawingIndexBox521.html#LM-1"><br>
</a></li>
<li><a href="LemDrawingIndexBox522.html#LM-2">LDW280-52000
(LM-2, Box 522)</a>. Used for ground testing, drop
testing.<br>
</li>
<li><a href="LemDrawingIndexBox523.html#LM-3">LDW280-53000
(LM-3, Box 523)</a>. Flown on Apollo 9.<br>
</li>
<li>LDW280-54000 (LM-4 through LM-9?, Box 525). See also
the <a href="LemDrawingMiscellaneous.html">LEM drawings from
non-NARA sources</a>.<br>
</li>
<li>LDW280-60000 (LM-10 through LM-15?, Box 528). See also
the <a href="LemDrawingMiscellaneous.html">LEM drawings from
non-NARA sources</a>.</li>
</ul>
<p>Our document library also contains some documents complementary
to these engineering drawings that you may find useful, such as
a few of <a href="links.html#Systems_Handbooks">the System
Handbooks</a>, Operations Handbooks, and Operational Data
Books specific to these LEMs. At this writing, for
example, there are the complete System Handbooks for LM-1, LM-3,
and LM-8, and some incomplete handbooks for various others of
the LEMs.<br>
</p>
<ul>
</ul>
<p>It's also worth noting that as an additional resource we've
made a <a href="LemDrawingIndex.tsv">LEM engineering-drawing
master-index file</a> that consolidates the indexes for all of
the LEM boxes into a single file. This is particularly
useful since drawings are often filed in the wrong boxes, for
whatever reason, and so it could otherwise be very tricky to
find specific drawing numbers (or drawing titles). You
probably will not be able to view this (very large) master-index
file within your browser, but you can instead download it onto
your local computer system. Once downloaded, you can do
various useful things with it, such as:<br>
</p>
<ul>
<li>View it as a text file.</li>
<li>Import it into a spreadsheet program such as Excel or
LibreOffice.</li>
<li>Write software yourself to process the index in whatever
manner suits you.<br>
</li>
</ul>
<p>Anyway, without further delay, here are index pages for the
individual LEM aperture-card boxes, to the extent that we've so
far scanned the boxes and put them online:<br>
</p>
<table cellspacing="2" cellpadding="2" border="1" align="center">
<tbody>
<tr>
<td valign="top">Box 241<br>
</td>
<td valign="top">Box 242<br>
</td>
<td valign="top">Box 243<br>
</td>
<td valign="top">Box 244<br>
</td>
<td valign="top">Box 245<br>
</td>
</tr>
<tr>
<td valign="top">Box 246</td>
<td valign="top">Box 247</td>
<td valign="top">Box 248</td>
<td valign="top">Box 249</td>
<td valign="top">Box 250</td>
</tr>
<tr>
<td valign="top">Box 251</td>
<td valign="top">Box 252</td>
<td valign="top">Box 253</td>
<td valign="top">Box 254</td>
<td valign="top">Box 255</td>
</tr>
<tr>
<td valign="top">Box 256</td>
<td valign="top">Box 257</td>
<td valign="top">Box 258</td>
<td valign="top">Box 259</td>
<td valign="top">Box 260</td>
</tr>
<tr>
<td valign="top">Box 261</td>
<td valign="top">Box 262</td>
<td valign="top">Box 263</td>
<td valign="top">Box 264</td>
<td valign="top">Box 265</td>
</tr>
<tr>
<td valign="top">Box 266</td>
<td valign="top">Box 267</td>
<td valign="top">Box 268</td>
<td valign="top">Box 269</td>
<td valign="top">Box 270</td>
</tr>
<tr>
<td valign="top">Box 271</td>
<td valign="top">Box 272</td>
<td valign="top">Box 273</td>
<td valign="top">Box 274</td>
<td valign="top">Box 275</td>
</tr>
<tr>
<td valign="top">Box 276</td>
<td valign="top">Box 277</td>
<td valign="top">Box 278</td>
<td valign="top">Box 279</td>
<td valign="top">Box 280</td>
</tr>
<tr>
<td valign="top">Box 281</td>
<td valign="top">Box 282</td>
<td valign="top">Box 283</td>
<td valign="top">Box 284</td>
<td valign="top">Box 285</td>
</tr>
<tr>
<td valign="top">Box 286</td>
<td valign="top">Box 287</td>
<td valign="top">Box 288</td>
<td valign="top">Box 289</td>
<td valign="top">Box 290</td>
</tr>
<tr>
<td valign="top">Box 291</td>
<td valign="top">Box 292</td>
<td valign="top">Box 293</td>
<td valign="top">Box 294</td>
<td valign="top">Box 295</td>
</tr>
<tr>
<td valign="top">Box 296</td>
<td valign="top">Box 297</td>
<td valign="top">Box 298</td>
<td valign="top">Box 299</td>
<td valign="top">Box 300<br>
</td>
</tr>
<tr>
<td valign="top">Box 301<br>
</td>
<td valign="top">Box 302</td>
<td valign="top">Box 303</td>
<td valign="top">Box 304</td>
<td valign="top">Box 305</td>
</tr>
<tr>
<td valign="top">Box 306</td>
<td valign="top">Box 307</td>
<td valign="top">Box 308</td>
<td valign="top">Box 309</td>
<td valign="top">Box 310<br>
</td>
</tr>
<tr>
<td valign="top">Box 311</td>
<td valign="top">Box 312</td>
<td valign="top">Box 313</td>
<td valign="top">Box 314</td>
<td valign="top">Box 315</td>
</tr>
<tr>
<td valign="top">Box 316</td>
<td valign="top">Box 317</td>
<td valign="top">Box 318</td>
<td valign="top">Box 319</td>
<td valign="top">Box 320</td>
</tr>
<tr>
<td valign="top">Box 321</td>
<td valign="top">Box 322</td>
<td valign="top">Box 323</td>
<td valign="top">Box 324</td>
<td valign="top">Box 325</td>
</tr>
<tr>
<td valign="top">Box 326</td>
<td valign="top">Box 327</td>
<td valign="top">Box 328</td>
<td valign="top">Box 329</td>
<td valign="top">Box 330</td>
</tr>
<tr>
<td valign="top">Box 331<br>
Various (Grumman vendor drawings)<br>
</td>
<td valign="top">Box 332<br>
Various (Grumman vendor drawings)<br>
</td>
<td valign="top">Box 332<br>
Various (Grumman vendor drawings)<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox502.html">Box
502</a><br>
LDW140-11430 to LDW270-53010<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox503.html">Box
503</a><br>
LDW270-53020 to LDW-280-10319<br>
</td>
</tr>
<tr>
<td valign="top"><a href="LemDrawingIndexBox504.html">Box
504</a><br>
LDW280-10321 to LDW280-10743<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox505.html">Box
505</a><br>
LDW280-10744 to LDW280-11216<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox506.html">Box
506</a><br>
LDW280-1127 to LDW280-11532<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox507.html">Box
507</a><br>
LDW280-11533 to LDW280-11869<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox508.html">Box
508</a><br>
LDW280-11870 to LDW280-14316<br>
</td>
</tr>
<tr>
<td valign="top"><a href="LemDrawingIndexBox509.html">Box
509</a><br>
LDW280-14317 to LDW280-16065<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox510.html">Box
510</a><br>
LDW280-16066 to LDW280-17381<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox511.html">Box
511</a><br>
LDW280-17382 to LDW280-17677<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox512.html">Box
512</a><br>
LDW280-17682 to LDW280-18029<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox513.html">Box
513</a><br>
LDW280-18030 to LDW280-18425<br>
</td>
</tr>
<tr>
<td valign="top"><a href="LemDrawingIndexBox514.html">Box
514</a><br>
LDW280-18426 to LDW280-18797<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox515.html">Box
515</a><br>
LDW280-18800 to LDW280-23074<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox516.html">Box
516</a><br>
LDW280-23075 to LDW280-23543<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox517.html">Box
517</a><br>
LDW280-23544 to LDW280-25661<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox518.html">Box
518</a><br>
LDW280-25662 to LDW280-28176<br>
</td>
</tr>
<tr>
<td valign="top"><a href="LemDrawingIndexBox519.html">Box
519</a><br>
LDW280-28178 to LDW280-28555<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox520.html">Box
520</a><br>
LDW280-28559 to LDW280-28885<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox521.html">Box
521</a><br>
LDW280-28887 to LDW280-51607<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox522.html">Box
522</a><br>
LDW280-51608 to LDW280-52663<br>
</td>
<td valign="top"><a href="LemDrawingIndexBox523.html">Box
523</a><br>
LDW280-52665 to LDW280-53279<br>
</td>
</tr>
<tr>
<td valign="top">Box 524</td>
<td valign="top">Box 525</td>
<td valign="top">Box 526</td>
<td valign="top">Box 527</td>
<td valign="top">Box 528</td>
</tr>
<tr>
<td valign="top">Box 529</td>
<td valign="top">Box 530</td>
<td valign="top">Box 531</td>
<td valign="top">Box 532</td>
<td valign="top">Box 533</td>
</tr>
<tr>
<td valign="top">Box 534</td>
<td valign="top">Box 535</td>
<td valign="top">Box 536</td>
<td valign="top">Box 537</td>
<td valign="top">Box 538</td>
</tr>
<tr>
<td valign="top">Box 539</td>
<td valign="top">Box 540</td>
<td valign="top">Box 541</td>
<td valign="top">Box 542</td>
<td valign="top">Box 543</td>
</tr>
<tr>
<td valign="top">Box 544</td>
<td valign="top">Box 545</td>
<td valign="top">Box 546</td>
<td valign="top">Box 547</td>
<td valign="top">Box 548</td>
</tr>
<tr>
<td valign="top">Box 549</td>
<td valign="top">Box 550</td>
<td valign="top">Box 551</td>
<td valign="top">Box 552</td>
<td valign="top">Box 553</td>
</tr>
<tr>
<td valign="top">Box 554</td>
<td valign="top">Box 555</td>
<td valign="top">Box 556</td>
<td valign="top">Box 557</td>
<td valign="top">Box 558</td>
</tr>
<tr>
<td valign="top">Box 559</td>
<td valign="top">Box 560</td>
<td valign="top">Box 561</td>
<td valign="top">Box 562</td>
<td valign="top">Box 563</td>
</tr>
<tr>
<td valign="top">Box 564</td>
<td valign="top">Box 565</td>
<td valign="top">Box 566</td>
<td valign="top">Box 567</td>
<td valign="top">Box 568</td>
</tr>
<tr>
<td valign="top">Box 569</td>
<td valign="top">Box 570</td>
<td valign="top">Box 571</td>
<td valign="top">Box 572</td>
<td valign="top">Box 573</td>
</tr>
<tr>
<td valign="top">Box 574</td>
<td valign="top">Box 575</td>
<td valign="top">Box 576</td>
<td valign="top">Box 577</td>
<td valign="top">Box 578</td>
</tr>
<tr>
<td valign="top">Box 579</td>
<td valign="top">Box 580</td>
<td valign="top">Box 581</td>
<td valign="top">Box 582</td>
<td valign="top">Box 583</td>
</tr>
<tr>
<td valign="top">Box 584</td>
<td valign="top">Box 585</td>
<td valign="top">Box 586</td>
<td valign="top">Box 587</td>
<td valign="top">Box 588</td>
</tr>
<tr>
<td valign="top">Box 589</td>
<td valign="top">Box 590</td>
<td valign="top">Box 591</td>
<td valign="top">Box 592</td>
<td valign="top">Box 593</td>
</tr>
<tr>
<td valign="top">Box 594</td>
<td valign="top">Box 595</td>
<td valign="top">Box 596</td>
<td valign="top">Box 597</td>
<td valign="top">Box 598</td>
</tr>
<tr>
<td valign="top">Box 599</td>
<td valign="top">Box 600<br>
</td>
<td valign="top">Box 601</td>
<td valign="top">Box 602</td>
<td valign="top">Box 603</td>
</tr>
<tr>
<td valign="top">Box 604</td>
<td valign="top">Box 605</td>
<td valign="top">Box 606</td>
<td valign="top">Box 607</td>
<td valign="top">Box 608</td>
</tr>
<tr>
<td valign="top">Box 609</td>
<td valign="top">Box 610</td>
<td valign="top">Box 611</td>
<td valign="top">Box 612</td>
<td valign="top">Box 613</td>
</tr>
<tr>
<td valign="top">Box 614</td>
<td valign="top">Box 615</td>
<td valign="top">Box 616</td>
<td valign="top">Box 617</td>
<td valign="top">Box 618</td>
</tr>
<tr>
<td valign="top">Box 619</td>
<td valign="top">Box 620</td>
<td valign="top">Box 621</td>
<td valign="top">Box 622</td>
<td valign="top">Box 623</td>
</tr>
<tr>
<td valign="top">Box 624</td>
<td valign="top">Box 625</td>
<td valign="top">Box 626</td>
<td valign="top">Box 627</td>
<td valign="top">Box 628</td>
</tr>
<tr>
<td valign="top">Box 629</td>
<td valign="top">Box 630</td>
<td valign="top">Box 631</td>
<td valign="top">Box 632</td>
<td valign="top">Box 633</td>
</tr>
<tr>
<td valign="top">Box 634</td>
<td valign="top">Box 635</td>
<td valign="top">Box 636</td>
<td valign="top">Box 637</td>
<td valign="top">Box 638</td>
</tr>
<tr>
<td valign="top">Box 639</td>
<td valign="top">Box 640</td>
<td valign="top">Box 641</td>
<td valign="top">Box 642</td>
<td valign="top">Box 643</td>
</tr>
<tr>
<td valign="top">Box 644</td>
<td valign="top">Box 645</td>
<td valign="top">Box 646</td>
<td valign="top">Box 647</td>
<td valign="top">Box 648</td>
</tr>
<tr>
<td valign="top">Box 649</td>
<td valign="top">Box 650</td>
<td valign="top">Box 651</td>
<td valign="top">Box 652</td>
<td valign="top">Box 653</td>
</tr>
<tr>
<td valign="top">Box 654</td>
<td valign="top">Box 655</td>
<td valign="top">Box 656</td>
<td valign="top">Box 657</td>
<td valign="top">Box 658</td>
</tr>
<tr>
<td valign="top">Box 659</td>
<td valign="top">Box 660</td>
<td valign="top">Box 661</td>
<td valign="top">Box 662</td>
<td valign="top">Box 663</td>
</tr>
<tr>
<td valign="top">Box 664</td>
<td valign="top">Box 665</td>
<td valign="top">Box 666</td>
<td valign="top">Box 667</td>
<td valign="top">Box 668</td>
</tr>
<tr>
<td valign="top">Box 669</td>
<td valign="top">Box 670</td>
<td valign="top">Box 671</td>
<td valign="top">Box 672</td>
<td valign="top">Box 673</td>
</tr>
<tr>
<td valign="top">Box 674</td>
<td valign="top">Box 675</td>
<td valign="top">Box 676</td>
<td valign="top">Box 677</td>
<td valign="top">Box 678</td>
</tr>
<tr>
<td valign="top">Box 679</td>
<td valign="top">Box 680</td>
<td valign="top">Box 681</td>
<td valign="top">Box 682</td>
<td valign="top">Box 683</td>
</tr>
<tr>
<td valign="top">Box 684</td>
<td valign="top">Box 685</td>
<td valign="top">Box 686</td>
<td valign="top">Box 687</td>
<td valign="top">Box 688</td>
</tr>
<tr>
<td valign="top"><br>
</td>
<td valign="top"><br>
</td>
<td valign="top"><br>
</td>
<td valign="top"><br>
</td>
<td valign="top"><a href="LemDrawingMiscellaneous.html">Scans
from non-NARA sources</a><br>
</td>
</tr>
</tbody>
</table>
<h1><a name="Additional_Engineering_Drawings"></a>Additional
Apollo Engineering Drawings<br>
</h1>
<p><a
href="NAADrawingNumberScheme.png"><img
src="NAADrawingNumberScheme-small.png"
title="Click to enlarge" alt="Click to enlarge" width="197"
height="320" border="2" align="right"></a>Beyond the Apollo
G&N System and LEM engineering drawings already covered,
some other Apollo engineering drawings have been accumulated
over time as well. I haven't created any nice index pages
for them, nor any index files that can be imported into a
spreadsheet program, so if you're interested you'll just have to
browse through them yourself ... or make an index and send it to
me! <br>
</p>
<ul>
<li>North American Aviation, "<a
href="Documents/CSM%20Functional%20Integrated%20System%20Schematics%20Block%20II%20Revision%20K.pdf">CSM
Functional Integrated System Schematics, Block II</a>", Rev.
K (1966). (This has NAA drawing number V34-900001, and
there are undoubtedly more copies in the NARA-SW aperture-card
boxes. But this particular scan is a really beautiful
PDF supplied by the University of Alabama, Huntsville, made
from a hardcopy at the U.S. Space & Rocket Center
archives. Thanks to Dan Kosko for finding this for us!)<br>
</li>
<li><a
href="https://archive.org/details/interfaceRevisionNoticesBox431_images">North
American Aviation / MIT Interface Revision Notices</a> (78
scans from aperture-card box 431). <br>
</li>
<ul>
</ul>
<li><a
href="https://archive.org/details/apertureCardBox472GrummanNARASW_images">Grumman
/ MIT Interface Revision Notices</a> (24 scans from
aperture-card box 472).</li>
<ul>
</ul>
<li><a
href="https://archive.org/details/apertureCardBox477Part2NARASW_images">Miscellaneous</a>
(535 scans from aperture-card box 477):</li>
<ul>
</ul>
<ul>
<ul>
</ul>
<li>Grumman / MIT Interface Revision Notices or Interface
Control Drawings.<br>
</li>
<ul>
</ul>
<li>North American Aviation drawings</li>
<ul>
</ul>
<li>North American Aviation / MIT Interface Revision Notices
or Interface Control Drawings<br>
</li>
<ul>
</ul>
<li>Technical Data Release or Revisions (TDRR's)</li>
<ul>
</ul>
<li>MIT MC-series documents</li>
</ul>
<li><a href="https://archive.org/details/v14_900017_images">Some
Block I CSM engineering drawings</a>. (38
scans.) There's also <a href="V14-900017%20Index.tsv">a
tab-delimited index of the scans</a>; perhaps they'll
eventually be added to the master index, but that has not
happened as of yet.<br>
</li>
<ul>
</ul>
</ul>
<p>You may ask why there is no extensive tranche of engineering
drawings for the CSM included? That's because the National
Archives has been scanning CSM aperture cards as a separate
effort, independent of the scanning of the LEM
engineering-drawing aperture cards. Because I'm not
involved in their scanning, I have not been able to arrange
access to those CSM scans. NARA has a plan to make all of
the digitized material available online ... someday.
Whether those materials will be free of charge or not, other
than the G&N and LEM scans, I do not know. At this
writing, only a fraction of the CSM cards have been scanned, and
I wouldn't be surprised if we have to wait a long, long time to
see them. So the only CSM scans presently available are
those that were acquired from other sources. <br>
</p>
<p>We do, however, have a breakdown of at least a portion of North
American's otherwise-mysterious numbering scheme for their CSM
drawings (to enlarge, click on on the image to the right).
I say it covers only a "portion" of the scheme because it
immediately fails to explain numbers like "V34-900001"
referenced at the top of this section ... presumably because
that document does not relate to a specific physical item
installed in the CSM. But this chart comes from North
American's much-more-extensive "<a
href="Documents/apollo_electrical_installation.pdf">Apollo
Electrical Installation</a>" manual, which has additional
information beyond just the chart.<br>
</p>
<ul>
<ul>
<ul>
</ul>
</ul>
<ul>
</ul>
</ul>
<ul>
</ul>
<p></p>
</div>
<blockquote> </blockquote>
<h1><a name="References"></a>References</h1>
<p>The official AGC/DSKY electro-mechanical drawings available to us
at the present time are these:</p>
<ul>
<li>Scans of Block II AGC electrical drawings preserved by Eldon
Hall, and then donated to the now-essentially-defunct
klabs.org. Contains most of the digital (as opposed to
analog) circuitry schematics for AGC p/n 2003993. <br>
</li>
<li>The "AGC Handbook", contributed by Don Eyles. Mostly
contains drawings for Block II AGC/DSKY part numbers <i>other</i>
than AGC p/n 2003993, and in some cases includes drawings other
than electrical schematics.<br>
</li>
<li>NARA SW aperture cards: An astounding array of Block
I/II AGC/DSKY electrical and mechanical drawings, and of G&N
drawings in general. Scanning them is an ongoing project.<br>
</li>
</ul>
Besides these primary sources, there are additional (sometimes
overlapping) essentially complete electrical schematics available
in:<br>
<ul>
<li>For Block I: <a href="Documents/apollocommandmodacel.pdf">AC
Electronics manual ND-1021041 volume 1</a> and <a
href="Documents/apollocommandmodacel_0.pdf">volume 2</a>.
Or,
the full-resolution scans (<a
href="https://archive.org/stream/apollocommandmodacel">volume
1</a> and <a
href="https://archive.org/stream/apollocommandmodacel_0">volume
2</a>).</li>
<li>For Block II and LM: <a
href="Documents/acelectroniclmma00acel.pdf">AC Electronics
manual ND-1021042 volume 1</a> and <a
href="Documents/acelectroniclmma00acel_0.pdf">volume 2</a>.
Or, the full resolution scan (<a
href="https://archive.org/details/acelectroniclmma00acel">volume
1</a> and <a
href="https://archive.org/stream/acelectroniclmma00acel_0">volume
2</a>). <br>
</li>
</ul>
These documents are theory-of-operation documents, which describe
the circuits textually and often provide useful information like
timing diagrams of what the circuits do. In the process of
providing this info, though, they provide the schematics themselves
as figured embedded within the text. In saying that the
schematics provided in the theory-of-operation documents are
"essentially complete", what I mean is that the schematics in these
volumes aren't precisely in the form of the original drawings, but
rather have been redrafted by AC Electronics to fit into the format
of their volumes. Thus, they are subject to mistakes (and
potentially, corrections) by AC Electronics, and cannot necessarily
be straightforwardly matched to specific drawing numbers or
revisions.<br>
<br>
Surprisingly, while we have schematics in one form or another for
all AGC/DSKY modules, though not necessarily in all of the different
forms or versions we like, and we have wiring diagrams for the DSKY
backplane into which its modules are inserted, we do <i>not</i>
have wiring diagrams for the AGC backplane. (See <a
href="#Basic_Partitioning_of_the_AGC">this section</a> for a
discussion of how the AGC circuitry is partitioned up.)
Nevertheless, we do have enough information about it to be useful,
compiled by two techniques: Firstly, the electrical schematics
for the individual circuit modules list "net names" for all of the
connector pins going from the module to the backplane, so we do know
how the modules were interconnected on the backplane; secondly,
physical AGCs can have their backplanes mapped by means of
continuity checking with an ohmmeter. Mike Stewart has put
together <a
href="https://github.com/virtualagc/agc_hardware/blob/block2/delphi.db">a
helpful sqlite database</a> and <a
href="http://apolloguidance.computer/pins">an interactive, online
form of it</a>, based on mapping out the backplane for AGC s/n 14.<br>
<br>
Other useful resources <i>may</i> be available in <a
href="links.html#AGC_electrical_schematics">the "AGC electrical
schematics" section of our document-library page</a>.<br>
<br>
Besides the AGC Handbook, additional information used for
cross-referencing the various drawings to specific AGC or DSKY part
numbers and/or serial numbers came from a couple of sources:<br>
<ul>
<li>Section 3.7 of the <a
href="Documents/NAS9-497_ApolloPrimaryGuidanceNavigationAndControlSystem.pdf">AC
Electronics
Final Report on Contract NAS9-497</a> and tables 7-IV and 7-VI
of the <a href="Documents/R-700-Volume-3-2nd-copy.pdf">Instrumentation
Labs Final Report on Contracts NAS9-153 and NAS9-4065</a> can
be used to relate many AGC and DSKY serial numbers to the
specific missions (or in some cases, other purposes) for which
they were used. In some cases, there is a discrepancy
between these two documents (e.g., which DSKYs were assigned to
LM-10), in which case the latter document was chosen to be
authoritative.<br>
</li>
<li>For Block I, <a
href="https://archive.org/stream/apollocommandmodacel_0#page/18/mode/1up">Table
8-III
in AC Electronics manual ND-1021041</a> can be used to obtain
drawing numbers for what we believe are AGC 1003700 and DSKYs
1003706 and 1003707.<br>
</li>
<li>For Block II and LM, tables <a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n481/mode/1up">8-II</a>
and <a
href="https://archive.org/stream/acelectroniclmma00acel#page/n197">3-IE</a>
in AC Electronics manual 1021042 can be used to obtain drawing
numbers of electrical schematics corresponding to several AGC
and DSKY assembly part numbers.</li>
</ul>
<p>Finally, you'll notice that almost every one of the original
electrical drawings includes the notation "INTERPRET DRAWING IN
ACCORDANCE WITH STANDARDS PRESCRIBED BY MIL-D-70327":<br>
</p>
<ul>
<li><a href="Documents/assist.dla.mil/MIL-D-70327.pdf">MIL-D-70327</a></li>
<li><a href="Documents/assist.dla.mil/MIL-D-70327-AMENDMENT-1.pdf">Amendment
1 for MIL-D-70327</a></li>
</ul>
<h1><a name="Further_Information_About_Scanned"></a>Further
Information About Scanned Engineering Drawings<br>
</h1>
<p>The <a href="#Browse_by_Drawing_Number">index pages</a> and <a
href="TipueSearch.html">search engine</a> for engineering
drawings are organized by <i>drawing number</i>. Most of
the G&N drawing numbers (from MIT/IL, AC Electronics,
Kollsman, etc.) are 7-digit numbers. Block I drawings
generally have numbers like 10<i>xxxxx</i>, while Block II
drawings generally have numbers like 20<i>xxxxx</i>, although
other drawings (such as Specification Control Drawings, SCDs) are
also mixed into that numbering system as 10<i>xxxxx</i> numbers as
well. Drawings for military specifications, from North
American, from Grumman, and so on, use other numbering systems.<br>
</p>
<p style="color: rgb(0, 0, 0); font-family: " times="" new=""
roman";="" font-size:="" medium;="" font-style:="" normal;=""
font-variant-ligatures:="" font-variant-caps:="" font-weight:=""
400;="" letter-spacing:="" orphans:="" 2;="" text-align:=""
start;="" text-indent:="" 0px;="" text-transform:="" none;=""
white-space:="" widows:="" word-spacing:=""
-webkit-text-stroke-width:="" text-decoration-style:=""
initial;="" text-decoration-color:="" initial;"="">In the simplest
case, a "drawing" is just a sheet of paper that has been scanned
and is presented as a single scanned image. However, there
are more-complicated cases as well, in which case a single drawing
number might be represented as several or even as many, many
scanned images:<br>
</p>
<ul style="color: rgb(0, 0, 0); font-family: " times="" new=""
roman";="" font-size:="" medium;="" font-style:="" normal;=""
font-variant-ligatures:="" font-variant-caps:="" font-weight:=""
400;="" letter-spacing:="" orphans:="" 2;="" text-align:=""
start;="" text-indent:="" 0px;="" text-transform:="" none;=""
white-space:="" widows:="" word-spacing:=""
-webkit-text-stroke-width:="" text-decoration-style:=""
initial;="" text-decoration-color:="" initial;"="">
<li>Drawings usually advance through several revisions, beginning
with "-", and progressing through "A", "B, "C", and so on.
If there are more than "Z" revisions, then you might see
revision codes like "AA", "AB", "AC", and so on. For
example, one drawing in the index goes up to revision
"DK". Some letters in the alphabet were not used for
revisions ("I", "O", "Q", "X").<br>
</li>
<li>Sometimes a drawing has multiple physical pages, called
"sheets". A 3-sheet drawing, therefore, might appear in
the index as three separate scans.</li>
<li>Most of our drawings were preserved as "microforms" attached
to "aperture cards" ... which means that a photograph was taken
of each sheet, and the photographic negatives were stored (and
eventually scanned) in place of the original paper
drawings. But if the original sheet was physically larger
than approximately an E-sized sheet of paper (44"×34"), it was
too large to be captured by a single photograph.
Therefore, it was photographed instead as a set of 2, 3, or 4
"frames", with frame 1 usually being the leftmost frame.
In those cases each scanned image is really a frame of a sheet,
rather than an entire sheet. Of course, today, we could
digitally process a set of scanned frames, and instead produce a
single image for each sheet. Perhaps that will be done for
our collection someday; presently, it has not been done for the
drawings indexed here, though it has been done for a subset of
them elsewhere on this site, when there has been a specific need
to do so.</li>
</ul>
<i>Most</i> (but not all) of the scans in the collection were
captured from aperture cards (held permanently at the U.S. National
Archives). Aperture cards are computer punch cards, into which
a photographic negative has been attached. The punch card
itself encodes metadata about the negative, such as its title, the
total number of sheets, the specific sheet number, the number of
frames in the sheet, the specific frame number, and so on.
Among the metadata fields on G&N cards is a "type" field; these
"types" aren't documented, as far as I know, but what I've noticed
is that they're interpreted as follows:<br>
<ul>
<li>Type 01: Actual engineering <i>drawings</i>.</li>
<li>Type 02: These are <i>documents</i>, with titles that
tend to read "PRODUCT SPECIFICATION, CONFIGURATION AND
ACCEPTANCE TEST REQUIREMENTS FOR <i>SOME ASSEMBLY NAME</i>".
In the index tables, I shorten this to just "CONFIG. &
ACCEPTANCE TEST REQS., <i>SOME ASSEMBLY NAME</i>". This
can be confusing because they usually (but not always) have
identical drawing numbers to the Type 01 drawings they're
associated with. They may provide a lot of supplemental
information such as expected voltage levels and waveforms that
the electrical drawings don't provide.</li>
<li>Type 03: I've only encountered a handful of these, but
they are documents with titles like "ASSEMBLY TEST PROCEDURE FOR
<i>SOME ASSEMBLY NAME</i>".</li>
<li>Type 05: These are also documents, and seem to have to
do with post-installation checkout procedures for equipment
(such as the G&N system) installed in the spacecraft.</li>
<li>Type 10: I've only seen a few of these, but they seem to
be engineering drawings indistinguishable from Type 01. I
suspect it's just a misprint for 01.<br>
</li>
</ul>
It is currently an ongoing effort on my part to scan all of the
boxes of aperture cards (nominally 1800 cards each) of Apollo
G&N drawings, and then conceivably the LM drawings from
Grumman. At present only a miniscule part of this scheme has
been completed, Where those complete box scans have become
available, they are the best places to browse drawings, since each
box tends to contain a range of consecutive drawing numbers.
Failing that, the <a href="AgcDrawingIndex.html">miscellaneous
index</a> contains mostly alternate scans of subsets of the cards
in the complete-box scans, but also contains a few hundred drawings
missing from the National Archives' boxes.<br>
<p style="color: rgb(0, 0, 0); font-family: " times="" new=""
roman";="" font-size:="" medium;="" font-style:="" normal;=""
font-variant-ligatures:="" font-variant-caps:="" font-weight:=""
400;="" letter-spacing:="" orphans:="" 2;="" text-align:=""
start;="" text-indent:="" 0px;="" text-transform:="" none;=""
white-space:="" widows:="" word-spacing:=""
-webkit-text-stroke-width:="" text-decoration-style:=""
initial;="" text-decoration-color:="" initial;"="">Note that the
descriptive text in the "Link" column of the various index tables
isn't really very significant. If the scan is simply a
stand-alone file on <a href="http://www.ibiblio.org/apollo">this
Virtual AGC Project website</a>, the link text reads "drawing",
while if it is instead a page within a larger batch of drawings at
<a href="https://archive.org/details/virtualagcproject">our
Internet Archive site</a>, then it is the page number within the
specific batch of scans it originally belonged to. There are
no references to drawings (if any) that may exist at unaffiliated
websites. Regardless, just ignore the text of the link and
click on it! <br>
</p>
<p style="color: rgb(0, 0, 0); font-family: " times="" new=""
roman";="" font-size:="" medium;="" font-style:="" normal;=""
font-variant-ligatures:="" font-variant-caps:="" font-weight:=""
400;="" letter-spacing:="" orphans:="" 2;="" text-align:=""
start;="" text-indent:="" 0px;="" text-transform:="" none;=""
white-space:="" widows:="" word-spacing:=""
-webkit-text-stroke-width:="" text-decoration-style:=""
initial;="" text-decoration-color:="" initial;"="">By the way, if
you should happen to download an image from the Internet Archive
site by using your browser's "save image as" function, or if you
try to download a PDF from there, if you're not careful you will
probably get a very low-quality (though usually adequate) image
rather then the full-resolution scan. To avoid or reduce
this quality reduction in downloading from our Internet Archive
site, you can do one of the following:<br>
</p>
<ul>
<li>Instead of downloading an <i>individual</i> image of a page,
you can download the full GENERIC RAW BOOK file. This file
is precisely what I uploaded to the Internet Archive in the
first place, and therefore is the maximum quality you're going
to be able to get. The downside is that since it contains
all of the pages in that particular batch of scans, it may be a
very large download.</li>
<li>Or similarly, you can download the SINGLE PAGE PROCESSED JP2
file instead. This has similar upsides and downsides as
the GENERIC RAW BOOK file but is often (though not always!) a
smaller file. There is a <i>theoretical</i> quality
reduction from the GENERIC RAW BOOK file, but it's unlikely to
be anything you could notice even if you try very hard to do so.<br>
</li>
<li>Or, you can still use the "save image as" function to save
just a single image, but before doing so you should "zoom in" a
few times (perhaps 3 times) rather than just using whatever
fills your screen. That fools the Internet Archive into
giving you the full image resolution. What you get will be
a JPEG file, which is theoretically of lower quality than the
images GENERIC RAW BOOK file, but you are unlikely to be able to
notice any difference visually. (For example, many of the
engineering-drawing images were scanned at a resolution of
10592×7392 pixels, and I find that if I just do a save-image-as
without any zooms I get just a 2648×1848 JPEG; if I zoom-in once
or twice, I get 5296×3696; if I zoom-in three or more times, I
get the full 10592×7392. Your mileage, of course, may
vary!)</li>
<li>Finally, at least if you're using the Google Chrome browser,
instead of using "save image as" you can right-click on the
image and use "open image in new tab" instead. In the
browser's URL bar, if you look at the very end of the URL,
you'll see "...&scale=<i>SOMENUMBER</i>&rotate=0".
Just change the scale to 1.0, hit return to load that URL — the
image you see on the screen will look exactly the same as
before! — and then use "save as". Again, you may have to
experiment with it a bit to get the results you want.</li>
</ul>
Finally, some of the electrical drawings in the index have been
manually transcribed into CAD files, using the open-source <a
href="http://kicad-pcb.org/">KiCad</a> schematic-capture
program. <a
href="https://github.com/virtualagc/virtualagc/tree/schematics">Those
transcriptions
can be found at our GitHub site</a>, but aren't explicitly linked
in the index, and <a href="KiCad">renderings of the CAD files as
images can be found here</a>. The latter will obviously be
of much higher legibility than the scans of the original drawings,
but also will potentially differ from them in some ways.
<ul>
</ul>
<ul>
</ul>
<ul>
</ul>
<h1><a name="Versioning"></a>Versioning the AGC and DSKY<br>
</h1>
The AGC and DSKY part-numbering scheme looked like this:<br>
<blockquote><i>PARTNUMBER-DASHNUMBER</i> <i>REVISION</i><br>
</blockquote>
<p>For example, Block II AGCs had <i>PARTNUMBER</i>s 2003100,
2003200, and 2003993, with <i>DASHNUMBER</i>s like -011, -021,
-031, and so on. <i>REVISION</i>s were letter codes, such
as A, B, C, etc., or else a dash (-) for "no revision". For
example,<br>
</p>
<blockquote>
<p>2003200-011A<br>
</p>
</blockquote>
<p>Given a part number for a particular AGC (or DSKY) model, the
part number then relates to a set of sub-assemblies (often
represented by electrical schematics or mechanical drawings), many
of which are circuit modules, which themselves may have varying
versions over time, and have part-numbers like<br>
</p>
<blockquote><i>PARTNUMBER</i> <i>REVISION</i><br>
</blockquote>
<p>For example, the AGC with p/n 2003200-011A contained, among other
things, an "oscillator module" which fit into a backplane socket
labeled B7, and which itself had a p/n 2005003E ... and naturally,
we have drawing 2005003E if you want to see it.<br>
</p>
<p>In general, those <i>DASHNUMBER</i>s cover different
configurations handled within the same engineering drawing.
For example, drawing 2003100 might cover both configurations -011
and -021, and you'd have to read the drawing itself to understand
how unit 2003100-021 differs from unit 2003100-011.<br>
</p>
<p>With rare exceptions, different <i>REVISION</i>s of a drawing do
not introduce any design changes within a specific configuration,
but may be used to cumulatively add a new configuration. In
other words, as long as a particular revision of a drawing
contains the configuration you're interested in, it doesn't really
matter (usually) that later revisions of a drawing may also exist,
because later revisions won't differ substantively as far as any
given configuration is concerned.<br>
</p>
<h1><a name="CAD_Files_and_Images"></a>CAD Transcriptions of Apollo
Engineering Drawings<br>
</h1>
<p>In addition to providing scans of original electrical and
mechanical drawings from the Apollo program, there is an ongoing
effort to transcribe these drawings into CAD files.<br>
</p>
<p>Such CAD transcriptions are made as faithfully visually to the
original as is feasible, given the capabilities of the CAD program
involved, as long as there is no compromise of electrical or
mechanical correctness. But realize that transcription is a
human effort, so transcribed CAD files may at first contain
errors; conversely, they may from time to time correct errors
present in the original drawings — naturally, though, with
suitable notes indicating that the change had been made, and
why. It has also been possible occasionally to reconstruct
some currently-missing drawings from the original Apollo Program.<br>
</p>
<h2><a name="Electrical_Drawings_"></a>Electrical Drawings<br>
</h2>
<p> </p>
<p>As far as electrical CAD files are concerned, no community effort
has developed to transcribe the electrical drawings into CAD, but
it now appears as though one isn't really needed since I'm sure I
can do them all myself ... eventually. You can simply treat
the CAD files as resources which appeared from nowhere, but which
you are free to use or modify for your own purposes.<br>
</p>
<p>To do so, the open-source <a href="http://kicad-pcb.org/">KiCad
electrical-design software</a> is used. It is available,
for free of course, on Windows, Mac OS X, and all of the major
flavors of Linux. The electrical schematics which have been
transcribed into CAD, or are in the process of being transcribed,
are stored in our GitHub repository:<br>
</p>
<div align="center">
<table cellspacing="2" cellpadding="2" align="center">
<tbody>
<tr>
<td valign="middle"><font size="+3"><span
style="font-family: sans-serif; font-size: 32px;
font-style: normal; font-variant-ligatures: normal;
font-variant-caps: normal; font-weight: 400;
letter-spacing: normal; text-align: start;
text-indent: 0px; text-transform: none; white-space:
normal; word-spacing: 0px; -webkit-text-stroke-width:
0px; text-decoration-style: initial;
text-decoration-color: initial; display: inline !
important; float: none;"> ⇨</span></font></td>
<td valign="middle"><span style="font-family: sans-serif;
font-size: 32px; font-style: normal;
font-variant-ligatures: normal; font-variant-caps:
normal; font-weight: 400; letter-spacing: normal;
text-align: start; text-indent: 0px; text-transform:
none; white-space: normal; word-spacing: 0px;
-webkit-text-stroke-width: 0px; text-decoration-style:
initial; text-decoration-color: initial; display: inline
! important; float: none;"></span><a
href="https://github.com/virtualagc/virtualagc/tree/schematics">Schematic
CAD Drawing Repository</a></td>
</tr>
</tbody>
</table>
</div>
<p>The CAD drawings are typically rendered as PNG images as well,
and <a href="KiCad/">provided separately</a> for convenient
browsing.<br>
</p>
<p>There's plenty of online material to help you get started with
KiCad, if you're inclined to do anything more with the CAD files
as such. Here's the executive summary of what you need to
know if you want to specifically work with our electrical
schematics in KiCad:<br>
</p>
<ul>
<li>It's best to use the <i>nightly build</i> of KiCad (presently
v6) rather than a stable version of it (presently v4 or v5), to
stay as up-to-date as possible with respect to the bug reports
we file.</li>
<li>What you find in our GitHub repository for any given
transcribed drawing is the following:</li>
<ul>
<li>A folder called Schematics/<i>DRAWINGNUMBER</i>/ containing
the files for the drawing. For example, the CAD files
for drawing 2005912B are in Schematics/2005912B/.<br>
</li>
</ul>
<ul>
<li>A KiCad project file called module.pro, which you will need
to open. <br>
</li>
<li>Once the project is open, you can run the schematic editor
(eeschema) from KiCad's menu. The schematic page that
opens up will <i>usually</i> look like 2 (or 1 or 3)
rectangular blocks. Each of the rectangular blocks
represents one of the original sheets of the drawing.
Just double-click on one of the blocks to see the schematic
for that page. <br>
</li>
<li>We use a grid size of 25 mils within the schematics.
You should set the grid size to 25 mils and stay with it.</li>
<li>Similarly, in the preferences, set the default line width to
20 mils.<br>
</li>
<li>Many of the drawings consist largely of open-collector
3-input NOR gates and oval-shaped pads, neither marked on the
schematics with reference designators, so you may need to rely
on notes within the schematic to know what's what.<br>
</li>
</ul>
<li>All of the symbol libraries for eeschema used in our CAD
drawings are <i>custom</i> libraries, and no standard KiCad
libraries are used. If you find that symbols are missing
in the schematics you load, you'll have to maneuver through
KiCad's menu system to individually enable all of the libraries
needed. These are the *.lib files in the GitHub
repository. There are a lot of them, primarily because of
visual and power-supply variations the schematics need for the
dual NOR-gate part; the main library, exclusive of the NOR
gates, is AGC_DSKY.lib.</li>
<li>You may also get warnings when loading a schematic about the
library versions having changed and asking if you want to
"recover" any symbols. The answer is that you do <i>not</i>
want to recover any of them, which at the present time means you
will need to uncheck the boxes next to every symbol it offers to
recover for you.</li>
<li>There's a lot of more-detailed information that may be useful
in the repository's <a
href="https://github.com/virtualagc/virtualagc/blob/schematics/README.md">README
file</a>.</li>
</ul>
<p>Though no help in transcription is really needed, help in
proof-reading and/or correcting the CAD files vs the original
drawings is welcomed, and you can contact me directly at the
address at the bottom of this page if you're interested.
Just proof-reading doesn't actually require using CAD or even
having expert electrical knowledge. It just involves
comparing two images like the ones below and seeing how they
differ from each other (click to enlarge):<br>
</p>
<p align="center"><a
href="klabs/history/agc_schematics_block2/logic/a13-1.jpg"><img
src="small-SCAN-2005269-.jpg" alt="Click to enlarge"
width="405" height="320" border="2"></a> <a
href="KiCad/2005269-/2005269--p1of1.png"><img
src="small-CAD-2005269--.png" alt="Click to enlarge"
width="414" height="320" border="2"></a></p>
<h2><a name="Mechanical_Drawings"></a>Mechanical Drawings</h2>
<h3><a name="2D_CAD_"></a>2D CAD<br>
</h3>
<p>We presently have no 2D CAD transcriptions of the original
AGC/DSKY mechanical drawings. If you would like to make some
2D CAD transcriptions of the mechanical drawings, I am happy to
accept them for inclusion in the collection. Any such CAD
files will be stored and made available in a folder in the
"mechanical" branch of our GitHub repository:<br>
</p>
<table cellspacing="2" cellpadding="2" align="center">
<tbody>
<tr>
<td valign="middle"><font size="+3"><span style="font-family:
sans-serif; font-size: 32px; font-style: normal;
font-variant-ligatures: normal; font-variant-caps:
normal; font-weight: 400; letter-spacing: normal;
text-align: start; text-indent: 0px; text-transform:
none; white-space: normal; word-spacing: 0px;
-webkit-text-stroke-width: 0px; text-decoration-style:
initial; text-decoration-color: initial; display: inline
! important; float: none;"> ⇨</span></font></td>
<td valign="middle"><span style="font-family: sans-serif;
font-size: 32px; font-style: normal;
font-variant-ligatures: normal; font-variant-caps: normal;
font-weight: 400; letter-spacing: normal; text-align:
start; text-indent: 0px; text-transform: none;
white-space: normal; word-spacing: 0px;
-webkit-text-stroke-width: 0px; text-decoration-style:
initial; text-decoration-color: initial; display: inline !
important; float: none;"></span><a
href="https://github.com/virtualagc/virtualagc/tree/mechanical/2D-CAD">2D
CAD Drawing Repository</a></td>
</tr>
</tbody>
</table>
<p>I would ask that submissions conform to the following:<br>
</p>
<ul>
<li>The 2D CAD files should be mechanically accurate with respect
to the original drawings.<br>
</li>
<li>If changes to the original design have been made to correct
errors in the original drawing (or for any other reason), you
should add notes to the CAD drawing explaining what has
happened, and why, when, and who made the change.<br>
</li>
<li>The files should be in DXF format.</li>
<li>The file naming should conform to the original Apollo drawing
number and revision. In other words, if you have
transcribed drawing 1234567A, it should be named 1234567A.dxf.<br>
</li>
<li>The files should be importable by <a
href="https://www.freecadweb.org/">FreeCAD open-source design
software</a>, and should be visually accurate with respect to
the original drawings, insofar as that is feasible, after being
so imported.</li>
</ul>
<h3><a name="3D_Models"></a>3D Models</h3>
Alternatively, people seem to be more interested the creation of
reusable 3D models of the various fabricated parts comprising the
AGC and/or DSKY. If you wish to make submissions of 3D models,
they'll be stored and made available in a folder in the "mechanical"
branch of our GitHub repository:<br>
<table cellspacing="2" cellpadding="2" align="center">
<tbody>
<tr>
<td valign="middle"><font size="+3"><span style="font-family:
sans-serif; font-size: 32px; font-style: normal;
font-variant-ligatures: normal; font-variant-caps:
normal; font-weight: 400; letter-spacing: normal;
text-align: start; text-indent: 0px; text-transform:
none; white-space: normal; word-spacing: 0px;
-webkit-text-stroke-width: 0px; text-decoration-style:
initial; text-decoration-color: initial; display: inline
! important; float: none;"> ⇨</span></font></td>
<td valign="middle"><span style="font-family: sans-serif;
font-size: 32px; font-style: normal;
font-variant-ligatures: normal; font-variant-caps: normal;
font-weight: 400; letter-spacing: normal; text-align:
start; text-indent: 0px; text-transform: none;
white-space: normal; word-spacing: 0px;
-webkit-text-stroke-width: 0px; text-decoration-style:
initial; text-decoration-color: initial; display: inline !
important; float: none;"></span><a
href="https://github.com/virtualagc/virtualagc/tree/mechanical/3D-models">3D
Model Repository</a></td>
</tr>
</tbody>
</table>
<br>
I'd like any submissions to conform to the following requirements:<br>
<ul>
<li>Models must be provided in the form of <a
href="https://en.wikipedia.org/wiki/ISO_10303-21">STEP files</a>,
and may optionally be supplemented by a readme file that
contains any useful information about the model, yourself, the
change history, etc. At present, no additional file types
are desired or accepted.</li>
<li>File-naming convention:</li>
<ul>
<li>Case 1: If the model is intended to exactly represent
the original Apollo mechanical drawing, for example 1234567A,
then it should be named the same way, but with a ".stp"
extension: 1234567A.stp. Notice that both the
drawing <i>number</i> and <i>revision</i> are used. In
this case, the readme file can be omitted, but will be
accepted if supplied.<br>
</li>
<li>Case 2: If the model has been modified in some way —
perhaps because you believe you have improved it or fixed bugs
in it, or have modified it to be manufactured with different
materials — you should add some extra description within the
filename itself: 1234567A-<i>ExtraDescriptionOfChanges</i>.stp.
(I'd
also personally prefer that filenames don't contain spaces,
though hyphens and underlines are okay.) In this case,
you should definitely provide the extra readme file to cover
the changes in detail.</li>
<li>The optional readme file should be named identically to the
STEP file, but with the ".md" extension instead:
1234567A.md or 1234567A-<i>ExtraDescriptionOfChanges</i>.md.
The ".md" indicates that the file is in <a
href="https://www.markdownguide.org/basic-syntax/">"markdown"
format</a>, which means that it could still be a pure-text
file if you like, but can additionally include enhanced
formatting.<br>
</li>
</ul>
<li>The STEP files should be importable by <a
href="https://www.freecadweb.org/">FreeCAD open-source design
software</a>, though they can be created in any modeling
software you favor. Nevertheless, only STEP files are
accepted into the repository.</li>
</ul>
<h3><a name="Submissions"></a>Submissions</h3>
<p>The best procedure for making your submissions to the repository
is this:<br>
</p>
<ol>
<li>Create an account for <a href="https://github.com">GitHub</a>
if you don't already have one.</li>
<li>Log into your GitHub account.</li>
<li>If you don't already know how to create a "pull request" on
GitHub, <a
href="https://help.github.com/en/articles/creating-a-pull-request">read
this explanation of how to do so</a>. Basically, you
want to upload your files to the "2D-CAD" or "3D-models" folder
(whichever is appropriate) of <a
href="https://github.com/virtualagc/virtualagc/tree/mechanical">the
<b>mechanical</b> branch of the Virtual AGC GitHub repository</a>.
GitHub will then ask us to approve the operation, which we
presumably will if the requirement described above are met.<br>
</li>
</ol>
<ul>
</ul>
<h1><a name="Digital_Simulation_of_the_AGC_Electronic"></a>Digital
Simulation of the AGC Electronics</h1>
<p>Surprisingly, digital simulation of the electronics turns out not
to be incredibly difficult. Nevertheless, discussion of the
topic can be rather involved, so to keep this page relatively
short (really!), <a href="Verilog.html">a separate page is
devoted to discussing digital simulation</a>.<br>
</p>
<ul>
</ul>
<ul>
</ul>
<h1><a name="Basic_Partitioning_of_the_AGC"></a>Basic Partitioning
of the AGC Electronics<br>
</h1>
The Block II or LM AGC contains two trays of electronics, the A-tray
and the B-tray.<br>
<p> <br>
</p>
<div align="center"><img src="SF9-PopulatedTrayA.jpg" alt=""
width="1398" height="869"></div>
<p> </p>
<p>The trays contain connectors allowing A to be connected to B, or
vice-versa, and to the outside world. Each tray also
contains a "backplane" into which electronics modules can be
plugged. The A-tray modules have designations like A1, A2,
..., A31, while the B-tray modules have designations like B1, B2,
..., B17.<br>
</p>
<div align="center"><img src="SF9-PartiallyExposedTrayB.jpg" alt=""
width="1137" height="570"></div>
<p>Each of these modules has an associated drawing. For
example, in the 2003200-011 AGC, module A1 (the "scaler" module)
has electrical drawing 2005259A. In other words, each module
is considered to comprise a single circuit, with a unique (though
possibly multi-sheet) drawing.<br>
</p>
<p>Modules A1 - A24 consist entirely of "logic": i.e., their
electrical drawings consist entirely of NOR-gates and the
connectors for plugging the modules into the
backplane. For this reason, I suppose, the
drawings aren't called "schematics", but are often given the
special name "LOGIC FLOW DIAGRAMS". But they're schematics
anyway. Modules A25 - A31 and B1 - B17 are entirely analog
in nature and are specifically called "SCHEMATICS".<br>
</p>
<p>As far as the construction of the circuitry is concerned, three
basic techniques were intermixed:<br>
</p>
<ul>
<li>Logic-flow module (A1 - A24) construction changed over time:</li>
<ul>
<li>Early 2003100 AGCs: The components of a module were
partitioned into 4 "quadrants", and the components of each
quadrant were mounted on a multilayer nickel ribbon. The
4 ribbons themselves were also interconnected at various
strategic spots. This design proved not to work properly
because of excessive interconnection delays due to the
properties of the ribbon, though as far as I know, the design
was basically sound in other respects and should still work if
a better interconnection technique is used. The picture
below is of a logic module with just such a nickel ribbon<br>
</li>
</ul>
</ul>
<div align="center"><img alt="Module with nickel-ribbon logic"
src="nickel_ribbon_logic.png" width="1350" height="414"><br>
</div>
<ul>
<ul>
<li>2003993, 2003200, and later 2003100 AGCs: Each module
contains two multilayer circuit boards, though I've chosen to
show you only one of them in the image below. We'd see
the other one if we flipped the module over.<br>
</li>
</ul>
</ul>
<div align="center">
<blockquote><img src="SF9-A1-side.jpg" alt="" width="1338"
height="270"><br>
</blockquote>
</div>
<ul>
<ul>
</ul>
<li>Analog modules (A25 - A29, B1 - B17): These used
so-called "welded cordwood" construction. What that means
is that you have a metal block with holes in it, like Swiss
cheese; the components (such as resistors, capacitors,
transistors, etc.) are inserted into the holes in the block,
with their leads protruding from either side. Wires are
then welded (not soldered) to the leads to interconnect the
components. In the image below, note the nifty insert
providing reference designators for the components.<br>
</li>
</ul>
<div align="center"><img src="SF9-B8-flip-zoom.jpg" alt=""
width="1410" height="567"><br>
</div>
<ul>
<li>The backplane was wirewrapped.</li>
</ul>
<div align="center"><img src="SF9-PartialBackplane.jpg" alt=""
width="1383" height="814"><br>
</div>
<ul>
</ul>
<p>Of course, these details don't matter much in modern terms unless
you're <i>very</i> enthusiastic about building an AGC re-creation
and want to do it absolutely 100% authentically. If you
were, you would be defeated in the end by the fact that the
electronic components originally used, such as the dual
triple-input NOR gates, are no longer available in precisely the
form they were originally used. And while I haven't priced
ferrite memory lately, I expect that it's probably not terribly
cost-effective. <img src="smiley.png" alt="" width="16"
height="16"> Though, surprisingly, you can get junked
ferrite-memory systems from eBay; not from the AGC, naturally, but
perhaps close enough that they could be made to work if mined for
parts.<br>
</p>
<p>The pictures in this section, taken by Mike Stewart, are of
Jimmie Loocke's model 2003100-071 AGC, s/n 14. <br>
</p>
<ul>
</ul>
<h1><a name="Drawings_for_Block_I_AGC"></a>Supplemental Information
for the Block I AGC<br>
</h1>
<p> </p>
<ul>
</ul>
<ul>
</ul>
<div align="center"><a href="1003700-011.jpg"><img alt=""
title="Click to enlarge." src="1003700-011-small.jpg"
width="512" height="350" border="2" align="top"></a><br>
<i>Some modules in an actual 1003700-011 AGC. (Click to
enlarge.)<br>
<br>
</i> </div>
<br>
<table cellspacing="2" cellpadding="2" border="1" align="center">
<tbody>
<tr>
<th valign="middle" nowrap="nowrap">Module Description<br>
</th>
<th valign="middle">Related ND-1021041 Figures </th>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A1 - A16: Logic Flow Bit<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/113/mode/1up">Figure
4-60,
Scaler B</a>. <a
href="https://archive.org/stream/apollocommandmodacel#page/113/mode/1up"><br>
</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/127/mode/1up">Figure
4-65,
Sequence Generator Interrupt Service</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/174/mode/1up">Figure
4-98,
Register A Single Bit Position</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/179/mode/1up">Figure
4-101,
Register A</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/181/mode/1up">Figure
4-102,
Register Q</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/183/mode/1up">Figure
4-103,
Register Z</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/185/mode/1up">Figure
4-104,
Register LP</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/187/mode/1up">Figure
4-105,
Register B</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/191/mode/1up">Figure
4-106,
Registers S and SQ</a> (page 1)<a
href="https://archive.org/stream/apollocommandmodacel#page/191/mode/1up"><br>
</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/193/mode/1up">Figure
4-106,
Registers S and SQ</a> (page 2)</li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/195/mode/1up">Figure
4-107,
Register G</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/197/mode/1up">Figure
4-108,
Register G Service</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/201/mode/1up">Figure
4-110,
Adder (X and Y Registers - Bit Position 1, 2)</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/205/mode/1up">Figure
4-111,
Adder (X and Y) Service</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/211/mode/1up">Figure
4-113,
Write Amplifier</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/217/mode/1up">Figure
4-115,
Parity Logic</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/223/mode/1up">Figure
4-117,
Register IN 0</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/227/mode/1up">Figure
4-118,
Register IN 2</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/229/mode/1up">Figure
4-119,
Register IN 3</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/233/mode/1up">Figure
4-120,
Register OUT 0</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/235/mode/1up">Figure
4-121,
Register OUT 1</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/237/mode/1up">Figure
4-122,
Register OUT 3</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/243/mode/1up">Figure
4-124,
Register OUT 4</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/255/mode/1up">Figure
4-129,
Register OUT 2</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
<ul>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A17: Logic Flow C<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/100/mode/1up">Figure
4-55,
Read, Write, and Clear Timing Signals</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/177/mode/1up">Figure
4-100,
Addressable Registers, Read and Write Control</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/197/mode/1up">Figure
4-108,
Register G Service</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/215/mode/1up">Figure
4-114,
Parity Service</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/217/mode/1up">Figure
4-115,
Parity Logic</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/249/mode/1up">Figure
4-127,
Alarm Circuits</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
<ul>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A18: Logic Flow B<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/179/mode/1up">Figure
4-101,
Register A</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/181/mode/1up">Figure
4-102,
Register Q</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/183/mode/1up">Figure
4-103,
Register Z</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/185/mode/1up">Figure
4-104,
Register LP</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/187/mode/1up">Figure
4-105,
Register B</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/191/mode/1up">Figure
4-106,
Registers S and SQ</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/197/mode/1up">Figure
4-108,
Register G Service</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/205/mode/1up">Figure
4-111,
Adder (X and Y) Service</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/243/mode/1up">Figure
4-124,
Register OUT 4</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/300/mode/1up">Figure
4-144,
Counter Service Gates</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
<ul>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A19, A39: Interface<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/245/mode/1up">Figure
4-125,
Downlink Telemetry Parallel to Serial Converter</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/247/mode/1up">Figure
4-126,
Downlink Telemetry Bit Sync Counter</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/269/mode/1up">Figure
4-135,
Interface Module A19</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/271/mode/1up">Figure
4-136,
Interface Module A39</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/391/mode/1up">Figure
4-182,
Power Supply Failure Detection Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A20, A40: Interface<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/245/mode/1up">Figure
4-125,
Downlink Telemetry Parallel to Serial Converter</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/273/mode/1up">Figure
4-137,
Interface Module A20</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/275/mode/1up">Figure
4-138,
Interface Module A40</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A21: Logic Flow S<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/115/mode/1up">Figure
4-61,
Time Pulse Generator</a><br>
</li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/135/mode/1up">Figure
4-68,
Register A Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/137/mode/1up">Figure
4-69,
Register Q Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/138/mode/1up">Figure
4-70,
Register Z Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/139/mode/1up">Figure
4-71,
Register LP Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/141/mode/1up">Figure
4-72,
Register S Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/143/mode/1up">Figure
4-73,
Register B Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/145/mode/1up">Figure
4-74,
Register G Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/147/mode/1up">Figure
4-75,
Adder (Registers X and Y) Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/149/mode/1up">Figure
4-76,
Parity Logic Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/151/mode/1up">Figure
4-77,
Addressable Registers Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/152/mode/1up">Figure
4-78,
Control Pulse RSTRT</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/153/mode/1up">Figure
4-81,
Control Pulse WOVI/</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/154/mode/1up">Figure
4-83,
Control Pulse RSB</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/156/mode/1up">Figure
4-85,
Control Pulses RB1 and RB2</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/158/mode/1up">Figure
4-87,
Control Pulses TSGN/, TSGN2/, and TSGN3/</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/159/mode/1up">Figure
4-88,
Control Pulse RIC</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/163/mode/1up">Figure
4-91,
Control Pulses R22 and R24</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/164/mode/1up">Figure
4-93,
Control Pulse TOV/</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/215/mode/1up">Figure
4-114,
Parity Service</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/291/mode/1up">Figure
4-141,
Address Generator (Counter Priority)</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/307/mode/1up">Figure
4-147,
Address Generator (Interrupt Priority)</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
<ul>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A22: Logic Flow P<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/135/mode/1up">Figure
4-68,
Register A Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/137/mode/1up">Figure
4-69,
Register Q Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/138/mode/1up">Figure
4-70,
Register Z Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/139/mode/1up">Figure
4-71,
Register LP Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/143/mode/1up">Figure
4-73,
Register B Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/145/mode/1up">Figure
4-74,
Register G Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/147/mode/1up">Figure
4-75,
Adder (Registers X and Y) Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/149/mode/1up">Figure
4-76,
Parity Logic Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/151/mode/1up">Figure
4-77,
Addressable Registers Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/155/mode/1up">Figure
4-84,
Control Pulse TMZ/</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/156/mode/1up">Figure
4-85,
Control Pulses RB1 and RB2</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/158/mode/1up">Figure
4-87,
Control Pulses TSGN/, TSGN2/, and TSGN3/</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/197/mode/1up">Figure
4-108,
Register G Service</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/205/mode/1up">Figure
4-111,
Adder (X and Y) Service</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/253/mode/1up">Figure
4-128,
Scaler Fail Alarm Circuits</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/300/mode/1up">Figure
4-144,
Counter Service Gates</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/363/mode/1up">Figure
4-169,
Inhibit Gates</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A23: Logic Flow E<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/133/mode/1up">Figure
4-67,
Instruction Decoder</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/164/mode/1up">Figure
4-92,
G Generator</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/165/mode/1up">Figure
4-95,
Branch Flip-Flops</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/300/mode/1up">Figure
4-144,
Counter Service Gates</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A24: Logic Flow R<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/127/mode/1up">Figure
4-65,
Sequence Generator Interrupt Service</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/135/mode/1up">Figure
4-68,
Register A Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/138/mode/1up">Figure
4-70,
Register Z Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/139/mode/1up">Figure
4-71,
Register LP Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/143/mode/1up">Figure
4-73,
Register B Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/145/mode/1up">Figure
4-74,
Register G Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/147/mode/1up">Figure
4-75,
Adder (Registers X and Y) Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/149/mode/1up">Figure
4-76,
Parity Logic Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/151/mode/1up">Figure
4-77,
Addressable Registers Control Pulses</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/152/mode/1up">Figure
4-79,
Control Pulse NISQ</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/153/mode/1up">Figure
4-80,
Control Pulses WOVC/ and WOVR/</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/153/mode/1up">Figure
4-81,
Control Pulse WOVI/</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/154/mode/1up">Figure
4-82,
Control Pulses KRPT/, RRPA, and RSCT</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/154/mode/1up">Figure
4-83,
Control Pulse RSB</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/156/mode/1up">Figure
4-85,
Control Pulses RB1 and RB2</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/157/mode/1up">Figure
4-86,
Control Pulses ST1 and ST2</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/158/mode/1up">Figure
4-87,
Control Pulses TSGN/, TSGN2/, and TSGN3/</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/159/mode/1up">Figure
4-88,
Control Pulse RIC</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/161/mode/1up">Figure
4-89,
Control Pulse CTR</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/163/mode/1up">Figure
4-90,
Control Pulse TRSM/</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/164/mode/1up">Figure
4-94,
Control Pulse RB14</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/197/mode/1up">Figure
4-108,
Register G Service</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/215/mode/1up">Figure
4-114,
Parity Service</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/243/mode/1up">Figure
4-124,
Register OUT 4</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/307/mode/1up">Figure
4-147,
Address Generator (Interrupt Priority)</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A25: Logic Flow Q<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/127/mode/1up">Figure
4-65,
Sequence Generator Interrupt Service</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/131/mode/1up">Figure
4-66,
SQ Decoder and State Decoder</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/165/mode/1up">Figure
4-95,
Brach Flip-Flops</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/165/mode/1up">Figure
4-95,
Branch Flip-Flops</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/191/mode/1up">Figure
4-106,
Registers S and SQ</a> (page 1)<a
href="https://archive.org/stream/apollocommandmodacel#page/191/mode/1up"><br>
</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/193/mode/1up">Figure
4-106,
Registers S and SQ</a> (page 2)</li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A26: Logic Flow J<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/115/mode/1up">Figure
4-61,
Time Pulse Generator</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
<ul>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A27: Logic Flow D<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/205/mode/1up">Figure
4-111,
Adder (X and Y) Service</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/305/mode/1up">Figure
4-146,
Interrupt Priority Control, Input Logic</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/353/mode/1up">Figure
4-166,
Bank Register</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/359/mode/1up">Figure
4-167,
Bank Selector Gates</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A28: Logic Flow N<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/97/mode/1up">Figure
4-53,
Binary Dividers</a><br>
</li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/103/mode/1up">Figure
4-57,
Ring Counter Logic</a></li>
<li><a href="KiCad/1006552r-Fig-4-59.png">Figure 4-59,
Scaler A</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/117/mode/1up">Figure
4-62,
Start-Stop Logic</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/295/mode/1up">Figure
4-143,
Display and Load Logic</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
<ul>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A29: Logic Flow V<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/235/mode/1up">Figure
4-121,
Register OUT 1</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/249/mode/1up">Figure
4-127,
Alarm Circuits</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/283/mode/1up">Figure
4-140,
Counter Priority Control</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/361/mode/1up">Figure
4-168,
Set Selector Gates</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/363/mode/1up">Figure
4-169,
Inhibit Gates</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A30 - A31: Logic Flow H<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/283/mode/1up">Figure
4-140,
Counter Priority Control</a> (page 1)</li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/285/mode/1up">Figure
4-140,
Counter Priority Control</a> (page 2)</li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/287/mode/1up">Figure
4-140,
Counter Priority Control</a> (page 3)</li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A32: Logic Flow F<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/164/mode/1up">Figure
4-92,
G Generator</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/215/mode/1up">Figure
4-114,
Parity Service</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/249/mode/1up">Figure
4-127,
Alarm Circuits</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/283/mode/1up">Figure
4-140,
Counter Priority Control</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/291/mode/1up">Figure
4-141,
Address Generator (Counter Priority)</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/292/mode/1up">Figure
4-142,
Counter Command Logic</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/295/mode/1up">Figure
4-143,
Display and Load Logic</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A33 - A34: Logic Flow G<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/107/mode/1up">Figure
4-59
(sheet 1), Scaler A</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/109/mode/1up">Figure
4-59
(sheet 2), Scaler A</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/321/mode/1up">Figure
4-153,
Memory Cycle Timing - Erasable</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/351/mode/1up">Figure
4-165,
Memory Cycle Timing, Fixed</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
<ul>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A35: Logic Flow A<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/300/mode/1up">Figure
4-144,
Counter Service Gates</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/325/mode/1up">Figure
4-155,
Address Decoder</a> (page 1)</li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/327/mode/1up">Figure
4-155,
Address Decoder</a> (page 2)</li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/364/mode/1up">Figure
4-170,
Strand Gates</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A36: Logic Flow T<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/257/mode/1up">Figure
4-130,
Rate Control Logic</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/259/mode/1up">Figure
4-131,
Rate 1 Control</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/261/mode/1up">Figure
4-132,
Rate 2 Control</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/263/mode/1up">Figure
4-133,
Rate 3 Control</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/265/mode/1up">Figure
4-134,
Continuous Pulse Control</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/283/mode/1up">Figure
4-140,
Counter Priority Control</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A37: Logic Flow L<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/161/mode/1up">Figure
4-89,
Control Pulse CTR</a>. <a
href="https://archive.org/stream/apollocommandmodacel#page/161/mode/1up"><br>
</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/165/mode/1up">Figure
4-95,
Branch Flip-Flops</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/223/mode/1up">Figure
4-117,
Register IN 0</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/249/mode/1up">Figure
4-127,
Alarm Circuits</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/283/mode/1up">Figure
4-140,
Counter Priority Control</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/305/mode/1up">Figure
4-146,
Interrupt Priority Control, Input Logic</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/307/mode/1up">Figure
4-147,
Address Generator (Interrupt Priority)</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A38: Logic Flow M<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/191/mode/1up">Figure
4-106,
Registers S and SQ</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/227/mode/1up">Figure
4-118,
Register IN 2</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/229/mode/1up">Figure
4-119,
Register IN 3</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/233/mode/1up">Figure
4-120,
Register OUT 0</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/235/mode/1up">Figure
4-121,
Register OUT 1</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/245/mode/1up">Figure
4-125,
Downlink Telemetry Parallel to Serial Converter</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/247/mode/1up">Figure
4-126,
Downlink Telemetry Bit Sync Counter</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/255/mode/1up">Figure
4-129,
Register OUT 2</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A39: Interface<br>
</td>
<td valign="middle">(See A19)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A40: Interface<br>
</td>
<td valign="middle">(See A20)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B2 - B4: Power Switch
Module<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/383/mode/1up">Figure
4-178,
+3 Volt Power Supply</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/385/mode/1up">Figure
4-179,
+13 Volt Power Supply</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/387/mode/1up">Figure
4-180,
Standby Circuit</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle">B5: Filter <br>
</td>
<td valign="top">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/381/mode/1up">Figure
4-177,
Primary Power Filter</a> </li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B6: AGC Clock Osc<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/93/mode/1up">Figure
4-52,
AGC Clock Oscillator Circuit</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B7: Driver Service<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/321/mode/1up">Figure
4-153,
Memory Cycle Timing - Erasable</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/329/mode/1up">Figure
4-156,
Selection Switches and Drivers</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/387/mode/1up">Figure
4-180,
Standby Circuit</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/391/mode/1up">Figure
4-182,
Power Supply Failure Detection Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B8: Current Switch<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/329/mode/1up">Figure
4-156,
Selection Switches and Drivers</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B9: Erasable Memory Stick<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/329/mode/1up">Figure
4-156,
Selection Switches and Drivers</a><br>
</li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B10 - B11: Erasable
Drivers<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/329/mode/1up">Figure
4-156,
Selection Switches and Drivers</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/333/mode/1up">Figure
4-157,
Inhibit Line Drivers</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B12: Power Supply Control<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/383/mode/1up">Figure
4-178,
+3 Volt Power Supply</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/385/mode/1up">Figure
4-179,
+13 Volt Power Supply</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/391/mode/1up">Figure
4-182,
Power Supply Failure Detection Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B13 - B14: Erasable Sense
Amplifiers<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/335/mode/1up">Figure
4-158,
Sense Amplifier and Voltage Source</a><br>
</li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B21 - B24, B28 - B29: Rope
Memory<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/365/mode/1up">Figure
4-171,
Rope and Strand Selectors</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/369/mode/1up">Figure
4-172,
Fixed Memory Inhibit Drivers and Return Circuits</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/371/mode/1up">Figure
4-173,
Fixed Memory Set Drivers and Return Circuits</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/373/mode/1up">Figure
4-174,
Fixed Memory Reset Drivers and Return Circuits</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/377/mode/1up">Figure
4-175,
Sense Amplifier and Voltage Source</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B26 - B27: Rope Sense
Amplifiers<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/377/mode/1up">Figure
4-175,
Sense Amplifier and Voltage Source</a> </li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B28 - B29: Rope Memory<br>
</td>
<td valign="middle">(See B21 - B24)<br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B30: Rope Strand Select<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/338/mode/1up">Figure
4-159,
Strobe Driver</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/365/mode/1up">Figure
4-171,
Rope and Strand Selectors</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B31: Strand Gate<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel#page/253/mode/1up">Figure
4-128,
Scaler Fail Alarm Circuits</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/365/mode/1up">Figure
4-171,
Rope and Strand Selectors</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/389/mode/1up">Figure
4-181,
Power Supply Filter Circuits</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/391/mode/1up">Figure
4-182,
Power Supply Failure Detection Circuits</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B32 - B33: Rope Driver<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/369/mode/1up">Figure
4-172,
Fixed Memory Inhibit Drivers and Return Circuits</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/371/mode/1up">Figure
4-173,
Fixed Memory Set Drivers and Return Circuits</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/373/mode/1up">Figure
4-174,
Fixed Memory Reset Drivers and Return Circuits</a></li>
</ul>
</td>
</tr>
</tbody>
</table>
<p> </p>
<ul>
</ul>
<br>
<h1><a name="Drawings_for_Block_I_Main_DSKY"></a>Supplemental
Information for the Block I Main and Navigation DSKY<br>
</h1>
<br>
<div align="center"><a href="1003563-031-1.jpg"><img alt=""
src="small-1003563-031-1.jpg" width="243" height="240"
border="2"></a> <a href="1003563-031-2.jpg"><img alt=""
src="small-1003563-031-2.jpg" width="254" height="240"
border="2"></a> <a href="1003563-031-3.jpg"><img alt=""
src="small-1003563-031-3.jpg" width="320" height="226"
border="2"></a> <a href="1003563-031-4.jpg"><img alt=""
src="small-1003563-031-4.jpg" width="263" height="240"
border="2"></a><br>
<i>Internal views of a 1003563-051 AGC. (Click to enlarge.</i></div>
<p> </p>
<br>
<table cellspacing="2" cellpadding="2" border="1" align="center">
<tbody>
<tr>
<th valign="middle" nowrap="nowrap">Module Description<br>
</th>
<th valign="middle">Related ND-1021041 Figures </th>
</tr>
<tr>
<td valign="top">D1 - D3: Decoding<br>
</td>
<td valign="top">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/509/mode/1up">Figure
4-233,
Relay Matrix Display Connections</a> (page 2). <br>
</li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/521/mode/1up">Figure
4-239,
Decoder, AGC Navigation Panel DSKY</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/523/mode/1up">Figure
4-240,
Relay Matrix, AGC Navigation Panel DSKY</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/525/mode/1up">Figure
4-241,
G & N System Relay Functions, AGC Navigation Panel
DSKY</a><br>
</li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/529/mode/1up">Figure
4-243,
Alarm Circuits, AGC Navigation Panel DSKY</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">D4 - D6: Decoding<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/499/mode/1up">Figure
4-230,
Decoder, AGC Main Panel DSKY</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/501/mode/1up">Figure
4-231,
Relay Matrix, AGC Main Panel DSKY</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/509/mode/1up">Figure
4-233,
Relay Matrix Display Connections</a> (page 2). <br>
</li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/511/mode/1up">Figure
4-234,
G and N System and Spacecraft Relay Functions, AGC
Main Panel DSKY</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/513/mode/1up">Figure
4-235,
Alarm Circuits, AGC Main Panel DSKY</a><br>
</li>
</ul>
</td>
</tr>
<tr>
<td valign="top">D7 - D10: Relays</td>
<td valign="top">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/507/mode/1up">Figure
4-233,
Relay Matrix Display Connections</a> (page 1)</li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/509/mode/1up">Figure
4-233,
Relay Matrix Display Connections</a> (page 2)</li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/523/mode/1up">Figure
4-240,
Relay Matrix, AGC Navigation Panel DSKY</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/525/mode/1up">Figure
4-241,
G & N System Relay Functions, AGC Navigation Panel
DSKY</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/529/mode/1up">Figure
4-243,
Alarm Circuits, AGC Navigation Panel DSKY</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">D11 - D14: Relays<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/501/mode/1up">Figure
4-231,
Relay Matrix, AGC Main Panel DSKY</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/507/mode/1up">Figure
4-233,
Relay Matrix Display Connections</a> (page 1)</li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/509/mode/1up">Figure
4-233,
Relay Matrix Display Connections</a> (page 2)</li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/511/mode/1up">Figure
4-234,
G and N System and Spacecraft Relay Functions, AGC
Main Panel DSKY</a></li>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/513/mode/1up">Figure
4-235,
Alarm Circuits, AGC Main Panel DSKY</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="top">D15: Power Supply<br>
</td>
<td valign="top">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/516/mode/1up">Figure
4-236,
Power Supply, AGC Main Panel DSKY</a>. </li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">D16: Power Supply<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/516/mode/1up">Figure
4-236,
Power Supply, AGC Main Panel DSKY</a><br>
</li>
</ul>
</td>
</tr>
<tr>
<td valign="top">D17: Keyboard<br>
</td>
<td valign="top">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/519/mode/1up">Figure
4-238,
AGC Navigation Panel DSKY, Schematic Diagram</a></li>
</ul>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">D18: Keyboard<br>
</td>
<td valign="middle">
<ul>
<li><a
href="https://archive.org/stream/apollocommandmodacel_0#page/495/mode/1up">Figure
4-229,
Main Panel DSKY, Schematic Diagram</a></li>
</ul>
</td>
</tr>
</tbody>
</table>
<br>
<h1><a name="2003100-021"></a>Supplemental Information for LM/Block
II AGC p/n 2003100-021</h1>
<p>This is an interesting version of the AGC, in that the logic
circuitry was constructed in a very different fashion than later
dash numbers of 2003100 (and the later versions 2003200 and
2003993) were. Those later versions used multi-layer printed
circuit boards to hold the integrated circuits, whereas <i>this</i>
version interconnected them via a nickel ribbon. <a
href="Documents/HSI-25007.pdf">The nickel-ribbon design turned
out to have too much capacitance, resulting in excessive signal
delay, and the design didn't function in practice</a>.
This is what resulted in the introduction of multi-layer printed
circuit boards instead. That's not to say, of course, that
there's anything wrong with the electrical schematics for this
design, since the physical construction of the circuitry is
basically outside the scope of the electrical schematics.
I'm told that all existing functional 2003100 AGC units are of the
multi-layer printed-circuit variety.<br>
</p>
<p>In addition to the nickel-ribbon interconnect, the circuitry for
the various modules was actually divided into four separate
"quadrants" of circuitry, which were mostly rather independent but
did have some interaction with each other. Later designs
removed the concept of quadrants altogether.<br>
</p>
<p>Besides <a href="#Sources_of_Information">the reference sources</a>
mentioned earlier, <a href="Documents/apollolunarexcuracel_1.pdf">AC
Electronics
document ND-1021043 of March 10, 1966</a>, supposedly relates to
AGC p/n 2003100-021 (according to its Tables 3-I and 7-I), and its
Table 8-II lists all of the associated module drawings. But
I don't believe there are any differences between the circuitry it
presents and that presented by ND-1021042.<br>
</p>
<p>Finally, there's the question of "signal wiring diagrams".
These are related to the nickel-ribbon interconnect described
above. To understand what that is and how to read one, consult the
<a href="#Appendix:_Signal_Wiring_Diagrams">Appendix</a>. It
should be noted that because of the later reworking of the design
to replace the nickel-ribbon interconnect with a multi-layer
printed circuit board, the reference designators and pin numbering
from later versions is not closely related to numbering of this
version of the design.<br>
</p>
<h1><a name="Supplemental2003200"></a>Supplemental Information for
LM/Block II AGC p/n 2003200<br>
</h1>
<table cellspacing="2" cellpadding="2" border="1" align="center">
<tbody>
<tr>
<th valign="bottom" nowrap="nowrap">Module Description<br>
</th>
<th valign="bottom">Related ND-1021042 Figures</th>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A1: Scaler Module<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n292/mode/1up">4-120</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A2: Timer<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n286/mode/1up">4-119</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n292/mode/1up">4-120</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n306/mode/1up">4-122</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n114/mode/1up">4-159</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A3: S Q Register and
Decoding<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n306/mode/1up">4-122</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n322/mode/1up">4-128</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n326/mode/1up">4-129</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n340/mode/1up">4-131</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n352/mode/1up">4-132</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n322/mode/1up">4-221</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A4: Stage Branch Decoding<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n330/mode/1up">4-130</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n342/mode/1up">4-131</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n352/mode/1up">4-132</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n364/mode/1up">4-134</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n434/mode/1up">4-135</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n442/mode/1up">4-136</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n78/mode/1up">4-152</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n80/mode/1up">4-153</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A5: Cross Point Generator
I<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n352/mode/1up">4-132</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n364/mode/1up">4-134</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n434/mode/1up">4-135</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n67/mode/1up">4-147</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n106/mode/1up">4-156</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A6: Cross Point Generator
II<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n364/mode/1up">4-134</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n434/mode/1up">4-135</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n80/mode/1up">4-153</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n264/mode/1up">4-200</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n280/mode/1up">4-207</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A7: Service Gates<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n376/mode/1up">4-134</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n60/mode/1up">4-143</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n64/mode/1up">4-144</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n65/mode/1up">4-145</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n66/mode/1up">4-146</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n68/mode/1up">4-148</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n70/mode/1up">4-149</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n78/mode/1up">4-152</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n80/mode/1up">4-153</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n85/mode/1up">4-153B</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n100/mode/1up">4-155</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n182/mode/1up">4-175</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A8: 4 Bit Module<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n44/mode/1up">4-142</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n82/mode/1up">4-153A</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n282/mode/1up">4-208</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A9: 4 Bit Module<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n48/mode/1up">4-142</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n82/mode/1up">4-153A</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n182/mode/1up">4-175</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A10: 4 Bit Module<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n52/mode/1up">4-142</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n82/mode/1up">4-153A</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n182/mode/1up">4-175</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A11: 4 Bit Module<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n44/mode/1up">4-142</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n182/mode/1up">4-175</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A12: Parity and S Register<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n306/mode/1up">4-122</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n446/mode/1up">4-136</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n44/mode/1up">4-142</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n70/mode/1up">4-149</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n72/mode/1up">4-150</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n94/mode/1up">4-154</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n100/mode/1up">4-155</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n108/mode/1up">4-157</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A13: Alarms<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n294/mode/1up">4-120</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n310/mode/1up">4-124</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n114/mode/1up">4-159</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n146/mode/1up">4-166</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n322/mode/1up">4-221</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A14: Memory Timing and
Addressing<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n42/mode/1up">4-141</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n44/mode/1up">4-142</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n98/mode/1up">4-155</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n146/mode/1up">4-166</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n264/mode/1up">4-200</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n277/mode/1up">4-206</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n280/mode/1up">4-207</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n282/mode/1up">4-208</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n306/mode/1up">4-218</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A15: RUPT Service<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n358/mode/1up">4-133</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n42/mode/1up">4-141</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n44/mode/1up">4-142</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n88/mode/1up">4-153C</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n102/mode/1up">4-155A</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n122/mode/1up">4-163</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n284/mode/1up">4-209</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A16: In/Out I<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n160/mode/1up">4-172</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n186/mode/1up">4-176</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n190/mode/1up">4-178</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n192/mode/1up">4-179</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A17: In/Out II<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n98/mode/1up">4-155</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n160/mode/1up">4-172</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n166/mode/1up">4-174</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n188/mode/1up">4-177</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n190/mode/1up">4-178</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n210/mode/1up">4-185</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A18: In/Out III<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n294/mode/1up">4-120</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n310/mode/1up">4-124</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n160/mode/1up">4-172</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n162/mode/1up">4-173</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n200/mode/1up">4-181</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n212/mode/1up">4-186</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n222/mode/1up">4-190</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n306/mode/1up">4-218</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A19: In/Out IV<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n294/mode/1up">4-120</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n310/mode/1up">4-124</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n190/mode/1up">4-178</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n204/mode/1up">4-182</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n206/mode/1up">4-183</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n208/mode/1up">4-184</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n214/mode/1up">4-187</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n218/mode/1up">4-189</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A20: Counter Cell I<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n128/mode/1up">4-164</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A21: Counter Cell II<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n356/mode/1up">4-133</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n128/mode/1up">4-164</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n322/mode/1up">4-221</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A22: In/Out V<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n114/mode/1up">4-159</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n198/mode/1up">4-180</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n214/mode/1up">4-187</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n222/mode/1up">4-190</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A23: In/Out VI<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n294/mode/1up">4-120</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n88/mode/1up">4-153C</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n160/mode/1up">4-172</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n182/mode/1up">4-175</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n190/mode/1up">4-178</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n212/mode/1up">4-186</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n218/mode/1up">4-189</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n224/mode/1up">4-190</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A24: In/Out VII<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n294/mode/1up">4-120</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n306/mode/1up">4-122</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n310/mode/1up">4-124</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n436/mode/1up">4-135</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n85/mode/1up">4-153B</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n114/mode/1up">4-159</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n142/mode/1up">4-165</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n146/mode/1up">4-166</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n158/mode/1up">4-171</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n182/mode/1up">4-175</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n190/mode/1up">4-178</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n222/mode/1up">4-190</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B7: Oscillator<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/apollolunarexcuracel_0#page/209/mode/1up">4-118</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B8: Alarms<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/apollolunarexcuracel#page/n264/mode/1up">4-170</a></td>
</tr>
</tbody>
</table>
<h1><a name="2003993-111"></a>Supplemental Information for LM/Block
II AGC p/n 2003993<br>
</h1>
<br>
<table cellspacing="2" cellpadding="2" border="1" align="center">
<tbody>
<tr>
<th valign="bottom" nowrap="nowrap">Module Description<br>
</th>
<th valign="bottom">Related ND-1021042 Figures </th>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A1: Scaler Module<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n292/mode/1up">4-120</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A2: Timer<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n286/mode/1up">4-119</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n292/mode/1up">4-120</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n306/mode/1up">4-122</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n114/mode/1up">4-159</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A3: S Q Register and
Decoding<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n306/mode/1up">4-122</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n322/mode/1up">4-128</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n326/mode/1up">4-129</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n340/mode/1up">4-131</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n352/mode/1up">4-132</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n322/mode/1up">4-221</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A4: Stage Branch Decoding<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n330/mode/1up">4-130</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n342/mode/1up">4-131</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n352/mode/1up">4-132</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n364/mode/1up">4-134</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n434/mode/1up">4-135</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n442/mode/1up">4-136</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n78/mode/1up">4-152</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n80/mode/1up">4-153</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A5: Cross Point Generator
I<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n352/mode/1up">4-132</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n364/mode/1up">4-134</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n434/mode/1up">4-135</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n67/mode/1up">4-147</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n106/mode/1up">4-156</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A6: Cross Point Generator
II<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n364/mode/1up">4-134</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n434/mode/1up">4-135</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n80/mode/1up">4-153</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n264/mode/1up">4-200</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n280/mode/1up">4-207</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A7: Service Gates<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n376/mode/1up">4-134</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n60/mode/1up">4-143</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n64/mode/1up">4-144</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n65/mode/1up">4-145</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n66/mode/1up">4-146</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n68/mode/1up">4-148</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n70/mode/1up">4-149</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n78/mode/1up">4-152</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n80/mode/1up">4-153</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n85/mode/1up">4-153B</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n100/mode/1up">4-155</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n182/mode/1up">4-175</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A8: 4 Bit Module<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n44/mode/1up">4-142</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n82/mode/1up">4-153A</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n282/mode/1up">4-208</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A9: 4 Bit Module<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n48/mode/1up">4-142</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n82/mode/1up">4-153A</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n182/mode/1up">4-175</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A10: 4 Bit Module<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n52/mode/1up">4-142</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n82/mode/1up">4-153A</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n182/mode/1up">4-175</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A11: 4 Bit Module<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n44/mode/1up">4-142</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n182/mode/1up">4-175</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A12: Parity and S Register<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n306/mode/1up">4-122</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n446/mode/1up">4-136</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n44/mode/1up">4-142</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n70/mode/1up">4-149</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n72/mode/1up">4-150</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n94/mode/1up">4-154</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n100/mode/1up">4-155</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n108/mode/1up">4-157</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A13: Alarms<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n294/mode/1up">4-120</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n310/mode/1up">4-124</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n114/mode/1up">4-159</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n146/mode/1up">4-166</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n322/mode/1up">4-221</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A14: Memory Timing and
Addressing<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n42/mode/1up">4-141</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n44/mode/1up">4-142</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n98/mode/1up">4-155</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n146/mode/1up">4-166</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n264/mode/1up">4-200</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n277/mode/1up">4-206</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n280/mode/1up">4-207</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n282/mode/1up">4-208</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n306/mode/1up">4-218</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A15: RUPT Service<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n358/mode/1up">4-133</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n42/mode/1up">4-141</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n44/mode/1up">4-142</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n88/mode/1up">4-153C</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n102/mode/1up">4-155A</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n122/mode/1up">4-163</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n284/mode/1up">4-209</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A16: In/Out I<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n160/mode/1up">4-172</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n186/mode/1up">4-176</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n190/mode/1up">4-178</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n192/mode/1up">4-179</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A17: In/Out II<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n98/mode/1up">4-155</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n160/mode/1up">4-172</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n166/mode/1up">4-174</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n188/mode/1up">4-177</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n190/mode/1up">4-178</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n210/mode/1up">4-185</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A18: In/Out III<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n294/mode/1up">4-120</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n310/mode/1up">4-124</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n160/mode/1up">4-172</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n162/mode/1up">4-173</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n200/mode/1up">4-181</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n212/mode/1up">4-186</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n222/mode/1up">4-190</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n306/mode/1up">4-218</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A19: In/Out IV<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n294/mode/1up">4-120</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n310/mode/1up">4-124</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n190/mode/1up">4-178</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n204/mode/1up">4-182</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n206/mode/1up">4-183</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n208/mode/1up">4-184</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n214/mode/1up">4-187</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n218/mode/1up">4-189</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A20: Counter Cell I<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n128/mode/1up">4-164</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A21: Counter Cell II<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n356/mode/1up">4-133</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n128/mode/1up">4-164</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n322/mode/1up">4-221</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A22: In/Out V<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n114/mode/1up">4-159</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n198/mode/1up">4-180</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n214/mode/1up">4-187</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n222/mode/1up">4-190</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A23: In/Out VI<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n294/mode/1up">4-120</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n88/mode/1up">4-153C</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n160/mode/1up">4-172</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n182/mode/1up">4-175</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n190/mode/1up">4-178</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n212/mode/1up">4-186</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n218/mode/1up">4-189</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n224/mode/1up">4-190</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A24: In/Out VII<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n294/mode/1up">4-120</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n306/mode/1up">4-122</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n310/mode/1up">4-124</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel#page/n436/mode/1up">4-135</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n85/mode/1up">4-153B</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n114/mode/1up">4-159</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n142/mode/1up">4-165</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n146/mode/1up">4-166</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n158/mode/1up">4-171</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n182/mode/1up">4-175</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n190/mode/1up">4-178</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n222/mode/1up">4-190</a><br>
</td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A25 - A26: Interface<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n228/mode/1up">4-191</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n306/mode/1up">4-218</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n348/mode/1up">4-225</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n354/mode/1up">4-227</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A27 - A29: Interface<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n232/mode/1up">4-192</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">A30 - A31: Power Supply<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n312/mode/1up">4-219B</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n320/mode/1up">4-220B</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B1 - B6: Rope Memory<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n288/mode/1up">4-210</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n288/mode/1up">4-211</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n290/mode/1up">4-212</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n292/mode/1up">4-213</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n294/mode/1up">4-214</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B7: Oscillator<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel#page/n282/mode/1up">4-118</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B8: Alarms<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n322/mode/1up">4-221</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B9 - B10: Erasable Drivers<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n268/mode/1up">4-202</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B11: Current Switch<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n268/mode/1up">4-202</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B12: Erasable Memory<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n274/mode/1up">4-205</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B13: Sense Amplifier<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n272/mode/1up">4-204</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n274/mode/1up">4-205</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B14: Sense Amplifier<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n298/mode/1up">4-215</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n300/mode/1up">4-216</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B15: Strand Select<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n286/mode/1up">4-210</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n298/mode/1up">4-215</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">B16 - B17: Rope Driver<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n290/mode/1up">4-211</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n290/mode/1up">4-212</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n292/mode/1up">4-213</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n294/mode/1up">4-214</a></td>
</tr>
</tbody>
</table>
<br>
<h1><a name="Supplemental_Information_for_Block"></a>Supplemental
Information for Block II DSKY</h1>
<table cellspacing="2" cellpadding="2" border="1" align="center">
<tbody>
<tr>
<th valign="middle" nowrap="nowrap">Module Description<br>
</th>
<th valign="middle">Related ND-1021042 Figures</th>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">D1 - D6: Indicator Driver<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n348/mode/1up">4-225</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n350/mode/1up">4-226</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n354/mode/1up">4-227</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n358/mode/1up">4-229</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n360/mode/1up">4-230</a>,
<a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n362/mode/1up">4-231</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">D7: Power Supply Module<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n364/mode/1up">4-232</a></td>
</tr>
<tr>
<td valign="middle" nowrap="nowrap">D8: Keyboard Module<br>
</td>
<td valign="middle"><a
href="https://archive.org/stream/acelectroniclmma00acel_0#page/n345/mode/1up">4-224</a><br>
</td>
</tr>
</tbody>
</table>
<h1><a name="PartNumbers"></a>Appendix: Evolution of Block II AGC
Part Numbers</h1>
The way different part numbers of AGCs (or DSKYs) are related to one
another is that you start with a given assembly with a certain part
number (such as Block II AGC with p/n 2003100-011), then you apply
an Engineering Change Proposal, or ECP for short, such as ECP 322
(described as "computer wiring changes"), with the result that you
now have a different assembly p/n 2003100-021. <br>
<br>
The list below shows how all known Block II AGC part numbers are
interrelated according to the principle just mentioned. Many
of these changes clearly are not electrical in nature, or else refer
to intermediate or test versions of the AGC. Sometimes there
are multiple paths to get to the same part number, if the ECPs are
applied in different orders. For example, p/n 2003993-061 +
ECP 815 = p/n 2003993-071 + ECP 719 = p/n 2003993-111. I've
only bothered to show one such path below in the few cases where
that happens.<br>
<ul>
<li>p/n 2003100-011</li>
<ul>
<li>p/n 2003100-021 — p/n 2003100-011 + ECP 322 ("computer
wiring changes")</li>
<ul>
<li>p/n 2003100-081 — p/n 2003100-021 + ECP 474 ("manufacture
test connector jumpers to ground certain gate inputs")</li>
<li>p/n 2003100-031, -041, -051 — p/n 2003100-021 + ECP 301
("thermal instrumentation")</li>
<ul>
<li>p/n 2003100-061 — p/n 2003100-031 + ECP 474
("manufacture test connector jumpers to ground certain
gate inputs")</li>
<li>p/n 2003100-071 — p/n 2003100-041 + ECP 474
("manufacture test connector jumpers to ground certain
gate inputs")</li>
<li>p/n 2003100-081 — p/n 2003100-051 + ECP 474
("manufacture test connector jumpers to ground certain
gate inputs")</li>
</ul>
<li>p/n 2003200-011 — p/n 2003100-021 + ECP 176 ("computer
module vibration") + ECP 226 ("aluminum to magnesium
conversion of AGC trays") + ECP 254 ("computer multilayer
board layout") + ECP 257 ("redesign of rope and erasable
drivers") + ECP 258 ("redesign of power supply module") +
ECP 259 ("redesign of erasable memory") + ECP 324 ("sense
amplifier threshold voltage stability change") + ECP 351
("alarm module temperature stabilization of warning
integrator and improve oscillator fail alarm") + ECP 368
("improved power supply module relays") + ECP 402 ("clear
circuit driver modification") + ECP 403 ("strobe
adjustment") + ECP 470 ("random workmanship vibration")</li>
<ul>
<li>p/n 2003200-021 — p/n 2003200-011 + ECP 440 ("'clear
rope' driver circuit modification") + ECP 443
("replacement of short screws") + ECP 447 ("incorporation
of plastic pads under tray A&B covers") + ECP 460
("addition of jumper wires in tray A") + ECP 478 ("paint
exposed surfaces on mid-tray spacer")</li>
<ul>
<li>p/n 2003200-031 — p/n 2003100-021 + ECP 486 ("cut pins
on AGC power supply to remove 28VDC regulator")</li>
<ul>
<li>p/n 2003200-041 — p/n 2003200-031 + ECP 474
("manufacture test connector jumpers to ground certain
gate inputs")</li>
<ul>
<li>p/n 2003200-051 — p/n 2003200-041 + ECP 518
("standby change on computer") + ECP 564
("implementation of flat pack specifications ND
1002359A & ND 1002358B") + ECP 604
("incorporation of E-memory vibration pads")<br>
</li>
<ul>
<li>p/n 2003200-061 — p/n 2003200-051 + ECP 719
("alarm module modification, V-fail detection")<br>
</li>
</ul>
</ul>
<li>p/n 2003993-011 — p/n 2003200-031 + ECP 452 ("wiring
change to accommodate auxiliary memory unit") + ECP
474 ("manufacture test connector jumpers to ground
certain gate inputs") + ECP 485 ("redesign power
supply to remove 28VDC regulator") + ECP 501
("implementation of flight processing spec") + ECP 505
("implementation of flight processing spec ND-1002341
and new diode") + ECP 511 ("correction of computer
noise SCAFAL problem")</li>
<ul>
<li>p/n 2003993-021 — p/n 2003993-011 + ECP 518
("standby change on computer") + ECP 631 ("replace
RTV-102 with RTV-109")</li>
<ul>
<li>p/n 2003993-031 — p/n 2003993-021 + ECP 564
("implementation of flat pack specifications ND
1002359A & ND 1002358B") + ECP 604
("incorporation of E-memory vibration pads")</li>
<ul>
<li>p/n 2003993-061 — p/n 2003993-031 + ECP 719
("alarm module modification, V-fail detection")</li>
<ul>
<li>p/n 2003993-111 — p/n 2003993-061 + ECP 815
("install restart monitor")</li>
</ul>
<li>p/n 2003993-071 — p/n 2003993-031 + ECP 815
("install restart monitor")</li>
</ul>
<li>p/n 2003993-041 — p/n 2003993-021 + ECP 564
("implementation of flat pack specifications ND
1002359A & ND 1002358B") + ECP 604
("incorporation of E-memory vibration pads")</li>
<ul>
<li>p/n 2003993-051 — p/n 2003993-041 + ECP 719
("alarm module modification, V-fail detection")
</li>
<li>p/n 2003993-081 — p/n 2003993-041 + ECP 815
("install restart monitor")</li>
<ul>
<li>p/n 2003993-091 — p/n 2003993-081 + ECP 719
("alarm module modification, V-fail
detection")</li>
</ul>
</ul>
</ul>
</ul>
</ul>
</ul>
</ul>
</ul>
</ul>
</ul>
<p>Note that there is also an ECP 483 for p/n 203993 listed in Table
8-II of document ND-1021042 (from which the information above
came), but I haven't been able so far to find out what it is, nor
at what dash number of 2003993 it became effective. <br>
</p>
<h1> </h1>
<h1><a name="Electronics_Component_Part_Numbers"></a>Electronics
Component Part Numbers and their SCDs<br>
</h1>
We don't have an official document, in so far as I am aware, giving
the Instrumentation Lab's part numbers for electronics components
like resistors, capacitors, transistors, and so on. Many of
them are deducible from other documents, like the AGC Handbook
drawings. For example, from drawing 2005952-, we can find out
that part number 1006750-32 is a 1/4W 1K resistor with a 2%
tolerance, while part number 1010406-7 is an 8.2 μH 10% tolerance
R.F. coil. Mike Stewart (thanks, Mike!) has done a lot of that
for us, but the task is still incomplete.<br>
<br>
<center><iframe src="MITcomponents.html" style="width:80%;
height:50%;"></iframe></center>
<br>
The list above may not be <i>fully</i> up-to-date with respect to
the master list, which is actually <a
href="https://github.com/virtualagc/virtualagc/blob/schematics/MITcomponents.csv">in
our
GitHub repository</a>. If you have corrections or additions
to this table, I believe you can edit the table directly in GitHub,
though your changes won't go live unless we approve them.<br>
<br>
In addition to the raw list of part numbers above, we have the
Specification Control Drawings (SCDs) for most of them. In
modern terms you can think of the SCD as being like the data sheets
for the components, except that instead of being written by the
manufacturers, they are Instrumentation Lab drawings, and serve
roughly the same purpose. We have most of the SCDs in multiple
revisions, so if you're interested in that kind of thing, you can
see how the specifications evolved over time. If you want to
see them, look on <a href="AgcDrawingIndex.html">our AGC
engineering-drawing index page</a>.<br>
<h1><a name="Appendix:_Signal_Wiring_Diagrams"></a> Appendix: Signal
Wiring Diagrams for the Block II and the NOR-Gate Problem<br>
</h1>
<p><img alt="" src="typicalCircuitry.png" width="309" height="252"
align="right">This section describes an issue that affects only
so-called "logic flow diagrams" (rather than analog-circuitry
schematics), and only early Block II AGC models and CDUs.<br>
</p>
<p>First, an elementary introductory digression, for anyone who
isn't an electronics expert but has persevered in reading to this
point.<br>
</p>
<p>When designing electronic circuitry, it is customary to assign
each electrical component in the circuit a unique "reference
designator" (or "refd", pronounced REF-DEE, for short), and to
refer to the components by those refd's. The refd's can be
anything, but customarily they consist of a letter to indicate the
general type of component — R for resistors, C for capacitors, D
(or perhaps CR) for diodes, and so on — followed by a number to
indicate which specific component it is within the circuit.
For example, in the typical kind of circuit diagram shown to the
right, you see resistors R1 through R7, capacitor C3, transistors
Q1 through Q3, and so on.<br>
</p>
<p>Integrated circuits (IC's) typically have U as the alphabetical
prefix, thus you might have integrated circuits U1, U2, U3, etc.<br>
</p>
<p>One thing that happens sometimes is that a given component might
actually be a conveniently packaged-together collection of <i>several</i>
essentially interchangeable simpler parts. For example, a
"dual NOR gate" integrated circuit would be a device that provides
two separate NOR gates, which are independent of each other but
are packaged together to save space or cost or for some other
reason of convenience. When that happens, the overall
integrated circuit still has a U-based refd, perhaps U3, but the
two NOR-gates comprising it each have refd's of their own, which
would normally be U3A and U3B.<br>
</p>
<p><img src="SenseAmplifierCircuit.jpg" alt="" width="541"
height="393" align="right">The example of a NOR-gate wasn't
chosen arbitrarily. In fact, since integrated circuits were a
pretty new development during the early Apollo Program, and were
still suspiciously unreliable and quite expensive, the AGC
circuitry originally didn't use any of them. Eventually,
though, the relentless pressure to miniaturize forced integrated
circuits into the design. As it happens, the AGC ended up
using a single type of integrated circuit (the DSKY used none at
all), though it used <i>lots</i> of them. As you've
probably guessed, that one type of IC was in fact a dual
triple-input NOR gate.<br>
</p>
<p>(Actually, that's a bit of an over-simplification, though it's
largely true for our purposes. In fact, the Block II AGC
used dual NOR gate integrated circuits, as stated, but the Block I
AGC used integrated circuits containing a single NOR-gate
each. Besides that, the sense amplifier modules used
comparatively small numbers of sense-amplifier integrated
circuits, whose internal composition is depicted in the figure to
the right. The sense amplifier integrated circuit was
exactly as complex as a dual triple-input NOR gate integrated IC,
in that each of them contained 6 NPN transistors and 8 resistors
... which is just an interesting factoid and is neither here nor
there. For the purposes of our present discussion, neither
the Block I NOR gates nor the sense-amplifier ICs are of any
relevance whatever.)<br>
</p>
<p>I won't bore you by telling you about the general properties of
NOR gates, but to understand the discussion in this section you do
need to know a couple of different things about them.
Firstly, in the AGC schematics a NOR gate is symbolized either as<br>
</p>
<div align="center"><img alt="" src="NORgates.png" width="244"
height="43"><br>
<br>
</div>
<div align="left">and secondly, all of the three inputs of a NOR
gate are interchangeable, in the sense that if you swapped any two
of them, the behavior of the device would remain the same. (I
suppose it may also be worth noting that of the two NOR-gate
representations above, you can have two of the left-hand kind as
the A and B parts of a dual NOR gate, or two of the right-hand
kind, but not one of each.)<br>
<br>
What this is all leading up to is that some of the CDU and early
AGC (p/n 2003100 only) electrical schematic drawings:<br>
<ol>
<li>Do not list any ref's for NOR-gates, so we have no way of
knowing from the schematics which individual NOR gate is
packaged with any other into a dual-NOR IC; and</li>
<li>Do not list any pin numbers for the NOR-gate inputs, so we
have know way of knowing which of the interchangeable inputs
any given input signal is hooked up to.</li>
</ol>
<div align="left"><img alt="" src="numberedSchematic.png"
width="474" height="247" align="right"></div>
<p>To get a sense of this, to the right there are two versions of
a sample (nonsense) circuit consisting of NOR gates, one with
refd's and pin numbers, and one without. In the right-hand
version, we know, for example, that pin U1A-J is connected to
pins U1B-F, U2A-F, and U2B-F. In the left-hand version we
know that the output from one NOR gate is connected to some
input or other on each of the other NOR gates. Imagine
trying to repair or discuss the left-hand version!<br>
</p>
<p>As far as the operation of the circuit is concerned, of course,
it makes no difference at all whether or not those refd's or pin
numbers are there, because all of the NOR gates are
interchangeable and all of the inputs to them are
interchangeable, so the OUTPUT we get from any given INPUT is
still exactly the same.<br>
</p>
<p>In the same way, you personally may not care one way or the
other which specific NOR gate is used for any given purpose in
the AGC circuitry, nor may you care which input pin is which on
those NOR gates. If that's so, you don't need to read any
further ... just go back to looking at the schematics presented
above on this page and enjoy!<br>
</p>
<p>But the truth is that the original AGC developers did care
which NOR gate was which and what pin number was what ... it's
just that for some reason they didn't find it convenient to put
that information directly into some of the schematic diagrams
for AGC p/n 2003100, and hence they chose to provide it through
some other mechanism. That mechanism is the so-called
"signal wiring diagram", and each of the schematic drawings in
the AGC 2003100 containing NOR gates had an associated signal
wiring diagram. Below, there's a "typical" (actually,
slightly more legible than usual) portion of a signal wiring
diagram:<br>
</p>
<div align="center"><img alt=""
src="typicalSignalWiringDiagram.jpg" width="1328" height="645"></div>
<p>You may be forgiven for thinking that this makes the situation
even more confusing to deal with, particularly since you are
quite correct about it, but it helps if you know how to read
it! When you know how to read it, it tells you which
NOR-gates are paired into which in the dual NOR-gate IC's, which
of the pair is the "A" member of the duet and which is the "B"
member, and which pin numbers the signals are hooked up to.<br>
</p>
<p>It doesn't tell you exactly how to specify the refd's of the
dual-NOR IC's, but we know from other versions of the AGC
roughly how they did that, so we'll talk about that later.<br>
</p>
<p>The first thing to notice is that one side of the diagram is
marked as LEFT and the other as RIGHT. In this drawing,
LEFT is at the bottom and RIGHT is at the top, but in other
drawings that's reversed, so try to think only of LEFT and RIGHT
instead of bottom and top.<br>
</p>
<p>Next, notice the little numbers written along the LEFT or
bottom edge (39155, 39145, 39149, ...) and RIGHT or top edge
(39156, 19151, 39152, ...). Those numbers are actually
written on the NOR gates in the schematics, in lieu of refd's,
and each individual NOR gate is identified uniquely by these
numbers. These are called "gate numbers". So, a pair
of such gate numbers could uniquely specify a dual-NOR
gate. The RIGHT numbers are the "A" NOR gates, and the
numbers opposite them on the LEFT are the associated "B" NOR
gates within the same dual NOR IC. <br>
</p>
<p>Before talking about the other stuff written on the diagram,
let's talk a little more about the dual-NOR ICs. The AGC's
were 10-pin rectangular packages, with the pins on them
variously labeled either numerically or alphabetically,
depending on the purpose of the discussion. We might draw
it like so, with the "A" NOR gate on the left and the "B" NOR
gate on the right:<br>
</p>
<div align="center"><img alt="" src="dualNOR.png" width="311"
height="299"></div>
<p><br>
Ignore the fact that the NOR gates now look like little rocket
ships; that may or may not be significant. Rather, the
important things to note are that there are VCC and GND inputs
to power the device, that the "A" gate has pins 1-4 (or J, A, B,
C), and that the "B" gate has pins 6-9 (or D, E, F, K).<br>
</p>
<p>If you look along the bottom (LEFT) edge of the signal wiring
diagram, you'll see a repeating pattern (from left to right)
consisting of<br>
</p>
<ol>
<li>a small square</li>
<li>an even smaller circle</li>
<li>empty position<br>
</li>
<li>empty position</li>
<li>empty position<br>
</li>
<li>an oval with a number inside </li>
</ol>
<div align="left">
<div align="left">Similarly, along the top (RIGHT) edge of the
signal wiring diagram, you'll see a similar but slightly less
regular pattern of 6 positions:<br>
</div>
<div align="left">
<ol>
<li>small circle</li>
<li>empty position</li>
<li>empty position</li>
<li>empty position<br>
</li>
<li>position with several possible markings</li>
<li>position with several possible markings<br>
</li>
</ol>
</div>
What those represent in terms of the dual-NOR IC are:<br>
<ul>
<li>LEFT</li>
</ul>
<div align="center">
<div align="left">
<ol>
<ol>
<li>
<meta http-equiv="content-type" content="text/html;
charset=UTF-8">
pin 10 (VCC) <span style="color: rgb(51, 51, 51);
font-family: "Open Sans", "Helvetica
Neue", Helvetica, Arial, sans-serif; font-size:
14px; font-style: normal; font-variant-ligatures:
normal; font-variant-caps: normal; font-weight: 400;
letter-spacing: normal; orphans: 2; text-align:
left; text-indent: 0px; text-transform: none;
white-space: normal; widows: 2; word-spacing: 0px;
-webkit-text-stroke-width: 0px; background-color:
rgb(249, 249, 249); text-decoration-style: initial;
text-decoration-color: initial; display: inline
!important; float: none;">□ </span></li>
<li>
<meta http-equiv="content-type" content="text/html;
charset=UTF-8">
pin 9 (K), the output <span style="color: rgb(51, 51,
51); font-family: "Open Sans",
"Helvetica Neue", Helvetica, Arial,
sans-serif; font-size: 14px; font-style: normal;
font-variant-ligatures: normal; font-variant-caps:
normal; font-weight: 400; letter-spacing: normal;
orphans: 2; text-align: left; text-indent: 0px;
text-transform: none; white-space: normal; widows:
2; word-spacing: 0px; -webkit-text-stroke-width:
0px; background-color: rgb(249, 249, 249);
text-decoration-style: initial;
text-decoration-color: initial; display: inline
!important; float: none;">○ </span> </li>
<li>pin 8 (F), an input<br>
</li>
<li>pin 7 (E), an input<br>
</li>
<li>pin 6 (D), an input<br>
</li>
<li>a position unrelated to the dual-NOR</li>
</ol>
</ol>
<ul>
<li>RIGHT<br>
</li>
</ul>
</div>
<div align="left">
<div align="center">
<div align="left">
<div align="center">
<div align="left">
<ol>
<ol>
<li>
<meta http-equiv="content-type"
content="text/html; charset=UTF-8">
<span style="color: rgb(51, 51, 51);
font-family: "Open Sans",
"Helvetica Neue", Helvetica,
Arial, sans-serif; font-size: 14px;
font-style: normal; font-variant-ligatures:
normal; font-variant-caps: normal;
font-weight: 400; letter-spacing: normal;
orphans: 2; text-align: left; text-indent:
0px; text-transform: none; white-space:
normal; widows: 2; word-spacing: 0px;
-webkit-text-stroke-width: 0px;
background-color: rgb(249, 249, 249);
text-decoration-style: initial;
text-decoration-color: initial; display:
inline !important; float: none;"></span>pin
1 (J), output <span style="color: rgb(51, 51,
51); font-family: "Open Sans",
"Helvetica Neue", Helvetica,
Arial, sans-serif; font-size: 14px;
font-style: normal; font-variant-ligatures:
normal; font-variant-caps: normal;
font-weight: 400; letter-spacing: normal;
orphans: 2; text-align: left; text-indent:
0px; text-transform: none; white-space:
normal; widows: 2; word-spacing: 0px;
-webkit-text-stroke-width: 0px;
background-color: rgb(249, 249, 249);
text-decoration-style: initial;
text-decoration-color: initial; display:
inline !important; float: none;">○ </span></li>
<li>pin 2 (A), an input</li>
<li>pin 3 (B), an input</li>
<li>pin 4 (C), an input<br>
</li>
<li>a position unrelated to the dual-NOR</li>
<li>a position unrelated to the dual-NOR<br>
</li>
</ol>
</ol>
</div>
<div align="left">You'll note that for both LEFT and
RIGHT, the sixth position has nothing to do with the
NOR gates, in some signal-wiring diagrams you'll
find that what we're calling position 6 here
actually appears at position 1 and the other
positions are simply displaced downward by 1.
That won't affect our discussion at all, and in fact
you might not even notice it if it hadn't been
pointed out to you, so we'll just ignore that
nicety. We'll get to what those non-NOR things
are later, but the point to understand right now is
that 9 of each dual-NOR's 10 pins appear in a
regular manner along these edges, and are easily
associated with their gate numbers. (Pin 5,
GND, isn't explicitly shown on the diagram, and we
won't worry ourselves about it.)<br>
</div>
<div align="left"> <br>
What about those weird, snake-like horizontal lines
running lengthwise along the middle of the signal
wiring diagram? Wires! Where the wire
points downward, there's a connection along the
bottom edge of the diagram, whereas when it points
upward there's a connection along the top edge of
the diagram. In the image below, I've added
some false coloring to just one of those snakelike
lines to focus the attention on it:<br>
<br>
</div>
</div>
</div>
</div>
</div>
</div>
</div>
<div align="center"><img alt=""
src="coloredSignalWiringDiagram.jpg" width="1328" height="645"></div>
<p>So according to the description I just gave, the wire makes a
connection to the following:<br>
</p>
<ul>
<li>NOR-gate at location 39155, pin 9 (output of a "B" NOR gate)</li>
<li>NOR-gate at location 39107, pin 9 (output of a different "B"
NOR gate)</li>
<li>An oval with a <i>very</i> smudgy 111 written in it.
Maybe.<br>
</li>
</ul>
<p>Now, if you know anything about electronics, you may be worried
that the outputs of two different NOR gates are tied
together. Don't worry, though, these NOR-gates have
open-collector outputs (or more precisely, open-collector with a
pullup resistor to VCC), and so they can be tied together to
increase their drive capacity (or to effectively increase the
number of NOR inputs for a single output) without any problem.<br>
</p>
<p>Perhaps I should finally say what some of these non-NOR
markings along the edges are:<br>
</p>
<ul>
<li>A numbered oval is a pin on the connector from the circuit
to the AGC's backplane. In other words, a signal leaving
or entering the circuit.</li>
<li>A pointed box like <VCC> or <0V> is a
power-supply or ground connection.</li>
<li>A rectangular box with an alphanumeric label inside of it is
an "inter-quadrant" connection, and we'll get to that in a
moment.</li>
</ul>
<p>At any rate, the point is that this red wire represents two
NOR-gates tied together to drive connector pin 111. Now, I
didn't mention it before, but this signal wiring diagram happens
to be from <a href="AGCHandbook/A5-2005061D-1.jpg">sheet 1 of
drawing 2005061D</a>, and if we look at that drawing, we will
indeed find that connector pin 111 is being driven by NOR gates
39107 and 39155.<br>
</p>
<p>What is this "inter-quadrant" thing of which I spoke, and for
that matter, what is a "quadrant" anyway?<br>
</p>
<p>For these AGC modules, the connector from the module to the AGC
backplane has 4 rows of 69 pins each (numbered 1 to 71, but with
21 and 51 missing). Each one of those rows of pins
essentially has its own circuit associated with it, and these
separate circuits are called "quadrants". The concept of
the "quadrant" was used only for early dash numbers of the
2003100 AGC (such as the one we have schematics for!), and
disappeared for later 2003100 versions, and for the 2003200 and
2003993 AGC's, though much of the numbering of components on the
schematics remains tied to the quadrant concept even if the
quadrants themselves disappeared.<br>
</p>
<p>By "separate circuits", I mean logically separate rather than
physically separated onto different circuit boards, though
apparently that was originally what was tried. And
usually, the circuitry on the quadrants isn't <i>entirely</i>
logically independent of the circuitry on the other quadrants,
and in that case there have to be one or more electrical
connections between the quadrants of the module ... i.e.,
inter-quadrant connections.<br>
</p>
<p>In fact, the signal wiring diagram I've been showing you isn't
the complete diagram for drawing 2005061D, but simply the signal
wiring diagram for quadrant 1 of 2005061D. There are three
other quadrants, and therefore 3 other signal wiring diagrams
for this module as well. Most modules have a complete
complement of 4 quadrants, and thus have 4 signal wiring
diagrams associated with them. But some modules have less
quadrants and therefore less signal wiring diagrams.<br>
</p>
<p>So now all of the questions are answered except for
refd's. For that, I want to direct your attention just
above the row of gate numbers at the bottom edge of the signal
wiring diagram shown above, or just below the row of gate
numbers along the top edge. You'll see a row of tiny, tiny
numbers going from 1 (at the left) to 180 (at the right)
there. Or more accurately, you'll see rows of tiny smudges
that may or may not be numbers, but you can still see that there
are 180 of them. Let's call these things "smudge numbers",
for lack of a better term. The IC's are numbered
sequentially, starting at the end with the larger smudge
numbers, where we find U01, and moving toward the end with the
smaller smudge numbers, where we find U30.<br>
</p>
<p>Actually, there's some subtlety involve here. For
example, what happens if there's an open space, as there is in
our pictured signal wiring diagram at U23? Should we just
skip U23 in our numbering altogether, or should the next
position become U23 rather than U24? You could argue it
either way, but I'd vote for skipping U23 altogether, because it
helps preserve IC numbering across different hardware
versions. In other words, if a dual-NOR is removed or
added, it won't necessarily cause all of the refd's for the <i>other</i>
dual-NORs to change. But truthfully, we don't actually
know what the original designers did in this regard.<br>
</p>
<p>Another subtlety in the IC numbering is the quadrants:
The entire circuit module consists of 4 quadrants, and if we
followed the scheme just described, there would be 4 IC's
labeled U01, 4 labeled U02, and so on. Not good! So
in our CAD work we actually prefix the quadrant numbers to the
IC numbering. In other words, in quadrant 1, the IC's run
from U101 up to U130; in quadrant 2, the IC's run from U201 up
to U230; etc. Thus every IC ends up with a unique number
within the module, and we can still use that number to precisely
identify where it is located physically.<br>
</p>
<p>And finally, one last subtlety: Some of the quadrants
have signal wiring diagrams as shown, with LEFT on the bottom,
RIGHT on the top, and smudge numbers increasing from left to
right. Other quadrants are reversed, with RIGHT on the
bottom, LEFT on the top, and smudge numbers increasing from
right to left. My descriptions above are all still
correct, as long as you keep thinking of LEFT and RIGHT and
ordering of smudge numbers as I've urged, rather than thinking
of the top, bottom, right, and left edges of the signal wiring
diagram as you might otherwise be inclined to do. The
reason for this reversal seems to have to do with some of the
quadrants being on the <i>front</i> side, and some being on the
<i>back</i> side, with the numbering consequently mirror imaged.<br>
</p>
<h1><a name="Appendix:_Signal_Wiring_Diagrams_for_the"></a>Appendix:
Signal
Wiring Diagrams and the Block I AGC</h1>
<p><img src="NOR-TO-47.jpg" alt="" width="147" height="132"
align="left"><img src="NOR-TO-47-diag.jpg" alt="" width="464"
height="491" align="right">For the Block I AGC, problems
similar to those described in the preceding section exist,
though the problems and solutions are different in detail.
In fact, read the preceding section before reading this one so
that you can have some background for the discussion in this
section!<br>
</p>
<p>One problem that can thankfully be ignored in the Block I AGC
is that the NOR-gate integrated circuit contains a single
triple-input NOR gate, packaged in a TO-47 can, rather than two
independent NOR gates packaged together in a flatpack, as in the
Block II AGC. That simplifies a lot. You can see
both a photo of such a gate (to the left) and a diagram
elucidating its pinout and internal circuit (to the right).<br>
</p>
<p>A problem the Block I "logic flow diagrams" (schematics
containing NOR gates) have that the Block II doesn't have, is
that there were apparently multiple hardware generations of the
Block I AGC that were mechanically quite different. In
particular, both the backplane-connector pin numbers and the
means for identifying the NOR-gate components differed from one
hardware generation to the next. The schematic diagrams,
meanwhile, showed the connector pin numbers and gate
identification for multiple hardware generations, thus making
them a tad more confusing than they might have been otherwise.<br>
</p>
<p>We don't actually know much about these different hardware
generations, but here's our current thinking on the
subject. We think there were three separate Block I AGC
hardware generations, which <i>may</i> have differed as
follows:<br>
</p>
<ul>
<li>The "AGC 4" generation: Might have been a rack-mount
computer. I.e., not of a similar size or shape to flight
models.<br>
</li>
<li>The "AGC 4B" generation: Might have been the first
with integrated circuits, as opposed to NOR gates constructed
from discrete transistors and resistors as in the diagram to
the right (which represents the internal structure of the NOR
integrated circuit). Using integrated circuits would
have miniaturized the circuit. The substitution doesn't
affect functionality, so we'd expect software written for the
one generation to execute properly on the other generation.</li>
<li>The "AGC 5" generation: Might have been constructed
more-or-less the same was as the flight computers were.
I.e., in a similar form factor.</li>
</ul>
<img src="excerpt-1006545-.jpg" alt="" width="453" height="219"
align="left">For example, in the tiny excerpt from one of the
Block I electrical schematics to the left, consider the NOR gate
with the markings "2G5" and "65129". "2G5" was how the gate
was identified in generation "AGC 4", while "65129" was how it was
identified in generation "AGC 5", according to the notes (not
shown) written in the schematic itself. <br>
<br>
<div align="left">Similarly, consider the connector pin for the
backplane signal "MPO". It is marked both as pin #94 and
as pin #104. The former is for AGC 4, while the latter is for
AGC 5.<br>
</div>
<br>
However, the Block I AGC schematics have the same characteristics
as the early Block II schematics, in the sense that they do not
display pin numbers for the (interchangeable) <i> inputs</i> of
the NOR gates, nor do they indicate what we would think of as
reference designators for the NOR gates. Of course, since
there's was a single NOR gate per integrated circuit, the
gate-number markings (like "2G5" or "65129) could basically serve
double-duty as reference designators, and having a separate
reference designator doesn't really serve much purpose, so perhaps
there weren't any at all. Plus, each of the NOR gates in the
example to the left has a single input ... but from the figure
above, we know that pins 1, 3, and 5 of the NOR gate were all
interchangeable, so which input is the one being used? They
probably are <i>not</i> all the "middle" pin, pin #3, since that
wouldn't always have been the pin it was most convenient to
physically route a wire to. <br>
<br>
At any rate, since the schematic doesn't have this kind of info in
it, the information has to come from somewhere else. It must
instead be deduced instead from the so-called "wiring
diagrams". These Block I wiring diagrams, however, though
quite similar in concept were quite different in detail from the
Block II signal wiring diagrams described in the preceding
section. The image below is a wiring diagram for the Block I
"scaler" module, otherwise known as AGC modules A33 and A34.
(Identical modules were plugged into slots A33 and A34.) The
wiring diagram itself is drawing 1006127A, while the corresponding
electrical schematic drawing is 1006547G. The original
drawing was in black&white (at least, by the time <i>we</i>
got it), but I've added various color notations to it for the
purpose of this discussion.<br>
<br>
<div align="center"><a
href="BlockIWiringDiagram-1006127A-annotated.jpg"><img
src="BlockIWiringDiagram-1006127A-annotated-small.jpg"
title="Click to enlarge" alt="" width="512" height="387"
border="2"></a><br>
<i>(Click to enlarge)</i><br>
</div>
<br>
Perhaps the first thing to note is that there are two separate
circuits in this wiring diagram. There's the "even" half,
depicted on the left-hand side of this diagram, consisting of the
columns labeled<br>
<div align="center"> <img src="wd1-6.png" alt="" width="37"
height="36"> <img src="wd1-2.png" alt="" width="37"
height="36"> <img src="wd1-4.png" alt="" width="37"
height="36"><br>
</div>
and the "odd" half (the right-hand side of the diagram), with
columns labeled<br>
<div align="center"><img src="wd1-5.png" alt="" width="37"
height="36"> <img src="wd1-3.png" alt=""
width="37" height="36"> <img src="wd1-7.png"
alt="" width="37" height="36"><br>
</div>
Of those, <b>2</b> and <b>3</b> are intended to represent the
front sides of the circuits, while <b>4</b>, <b>6</b>, <b>5</b>,
and <b>7</b> (being mirror imaged) represent the back side of the
circuits.<br>
<br>
These two halves are independent of each other, in the sense that
the only electrical connections between the two are via the
backplane. In other words, if you wanted to connect a signal
in the left half of the circuit to one in the right half, the
signal would have to go out through the module's connector, onto
the AGC backplane, then back up into a different pin on the
module's backplane connector. There is a 142-pin connector
(two rows of 71 pins each) to the backplane, with the the even
half of the circuit using the even-numbered pins and the odd half
using the odd-numbered pins, and in the diagram the connector pins
are also depicted as circled numbers like<br>
<div align="center"><img src="wd1-connectorpins.jpg" alt=""
width="39" height="131"><br>
</div>
<br>
Each the two halves has 60 NOR gates, labeled in the diagram both
by a "CIRCUIT NUMBER" and a "POSITION NUMBER", and are depicted in
the diagram as objects like<br>
<div align="center"><img src="wd1-normal.png" alt="" width="43"
height="42"> <i>or</i> <img
src="wd1-expander.png" alt="" width="43" height="42"><br>
</div>
<p>The former are the normal NOR gates, while the latter are the
so-called "expander" or "fan-in" NOR gates, represented in the
electrical schematics by the following two symbols,
respectively:<br>
</p>
<p align="center"><img alt="" src="NORgates.png" width="244"
height="43"></p>
<p>As you can see, each of these NOR gates has 4 signals, as it is
supposed to, with the open circle being the output and the solid
circles being the three inputs. As as far as <i>which</i>
of the filled-in black circles represent <i>which</i> inputs to
the NOR gates, we don't actually have enough information about
how the wiring diagrams are interpreted to be able to
tell. On the basis of the fact that these circular objects
visually represent the bottom side of the NOR-gate TO-47 cans
(see the figure at the top right of this section), my
interpretation would be:<br>
</p>
<div align="center"><img src="wd1-pinout.jpg" alt="" width="110"
height="120"></div>
<p>Of course, a mirror image of this arrangement, or indeed any
other permutation of pins 1, 2, and 3 would logically be equally
possible.<br>
</p>
<p>Note too that some or all of the NOR-gate pins have solid black
lines going to them, and of course these represent the
wires. All of the fat, solid, black lines in the wiring
diagram are wires.<br>
</p>
<p>The final factoid needed to interpret the diagram is to note
that each of the circuit halves seems to have wires that exit to
the left or to the right, and then just stop in mid-air, so to
speak, without actually connecting to anything. Notice, however,
that the wires exiting to the left and the right are exactly
paired with each other: for each wire exiting to the left,
there's one at the exact same position vertically exiting to the
right. This is intended to mean that those two dangling
wires are connected together as the same signal. I've
added a couple of blue lines to the diagram to make this point
graphically.<br>
</p>
<p>Actually, to avoid being misleading, I should admit that it's a
little trickier than this sometimes. The true is that
there's not <i>necessarily</i> a unique match between the
dangling wires exiting to the left and those to the right, so
sometimes you have to work it out using the schematic as a
reference. The figure below is an excerpt from a different
signal-wiring diagram that shows this ambiguity. I can't
really give you any advice on resolving such ambiguities, other
than to say that if you trace through the wires, you'll
(hopefully always) find that one of the possible connections
makes no sense with respect to the associated schematic, and
that the other one does.<br>
</p>
<div align="center"><img alt=""
src="BlockIWiringDiagram-1006127A-ambiguous.jpg" width="786"
height="71"></div>
<p>Ignoring complications like that, which are fortunately in the
minority, let's work out an example in detail. Consider
the NOR-gate with CIRCUIT NUMBER "--039" at POSITION NUMBER "02"
at the upper left of the wiring diagram. (You'll have to
click on the wiring diagram image shown earlier to expand it, in
order to understand the description below.) In the wiring
diagram, we see that:<br>
</p>
<ul>
<li>The output of --039, pin 7, exits to the left, where it
wraps around and connects to a corresponding wire dangling at
the right, and eventually ends up at connector pin 02.</li>
<li> Input pin 1 of --039 comes from a signal that comes from or
goes to the following places:</li>
<ul>
<li>Output pin 7 of NOR gate --035.</li>
<li>Input pin 1 of NOR gate --037.</li>
</ul>
</ul>
<p>So ... how well does this correspond to what the corresponding
electrical schematic drawing, <a
href="https://archive.org/stream/BlockISchematics#page/n143/mode/1up">1006547G</a>,
says is supposed to be happening? Well, wonder no
more! Here's the relevant excerpt from the schematic, and
as you can see, it is exactly as our interpretation of the
wiring diagram says it ought to be:<br>
</p>
<div align="center"><img src="wd1-example.jpg" alt="" width="1061"
height="195"><br>
<div align="left"><br>
But finally, a word of caution: The match between
electrical schematics and their associated signal wiring
diagrams is not always as perfect as the explanation above
implies. Of course, the Apollo Program preceded the
availability of computerized CAD systems which could have
automatically generated error-free signal wiring diagrams (if
they were even needed at all!) directly from the
schematics. In other words, both the schematics and the
wiring diagrams had to be separately, manually drawn ...
naturally, we'd expect occasional errors just on that
account. But it's somewhat worse than that.
Consider the example we've been using, namely schematic
1006547 and associated wiring diagram 1006127. This
block of circuitry has NOR-gates labeled "--000" through
"--079", plus additional NOR gates in the range "--301" and
above. The schematic and wiring diagram match perfectly
for the range 000-079, but <i>completely differ </i>for the
range 301+, as if completely different circuits were being
described by the schematic and the wiring diagram. And
that may indeed be what happened, since the wiring diagram was
drawn in February 1963, some three months prior to the
schematic in May 1963. Possibly there had been second thoughts
about the partitioning of the circuitry into modules in the
interim. Thus where the schematics and wiring diagrams match,
we should feel confident in using the information we find in
the wiring diagrams to supplement what we find in the
schematics, but we need to be aware that they <i>may not</i>
match, and that we must be prepared to work from whichever one
of those two is "correct".<br>
<br>
All very well and good! But how do we know which, if
either, <i>is</i> correct? I suppose I'd generally vote
for the schematic, if only because the wiring diagram is a
much less satisfactory way of visualizing how the circuit
works. This is particular example of drawings 1006547
and 1006127, though, there are lots of circumstantial factors
that would make us choose the schematic over the wiring
diagram:<br>
<ul>
<li>The schematic was drawn 3 months later than the wiring
diagram, and is therefore more current.</li>
<li>We have 2 revisions of the wiring diagram vs 8 of the
schematic, so gross errors seem less likely to have
survived in the schematic than in the wiring diagram.</li>
<li>The documentation in AC Electronics ND-1021041 matches
the schematic rather than the wiring diagram.</li>
</ul>
<h1><a name="Appendix:_Software"></a>Appendix: Auxiliary
Software</h1>
<h2>Introduction<br>
</h2>
<p>Along with the various scanned engineering drawings, CAD
transcriptions, drawing indexes, assembly drilldowns, and
engineering-drawing search engine we provide, there's also a
certain amount of software available to help create and
maintain all of that data. Most of it is undoubtedly
of little use to anybody not intimately involved in such
maintenance. But there are a few programs, such as <a
href="#Navigate_the_Assembly_Hierarchy_">the drilldown.py
and drilldownCompare.py programs already described above</a>,
that can be of slightly wider (though still very
specialized) utility. <br>
</p>
<p>On that chance, this Appendix provides a very-brief rundown
of some of that additional software. Except where
otherwise stated, such software is generally found in the
software repository's "schematics" branch, in <a
href="https://github.com/virtualagc/virtualagc/tree/schematics/Scripts">the
Scripts/ folder</a>, so you can likely find programs there
that I choose not to mention here.<br>
</p>
<table width="100%" cellspacing="2" cellpadding="2" border="1">
<tbody>
<tr>
<th valign="middle" align="left">Program<br>
</th>
<th valign="middle" align="left">Brief Description<br>
</th>
<th valign="middle" align="left">More Information<br>
</th>
</tr>
<tr align="center">
<td colspan="3" rowspan="1" valign="middle"><i>Context:
Transcription to KiCad of G&N electrical
schematics</i><br>
</td>
</tr>
<tr>
<td valign="middle">MakeConnector.py</td>
<td valign="middle">Creation of custom KiCad schematic
symbols for connectors.</td>
<td valign="middle"><a
href="https://github.com/virtualagc/virtualagc/blob/schematics/Scripts/MakeConnector.py">As
far as how to specify the characteristics of a
particular connector configuration, see the comments
in the code itself</a>. What the program
actually creates is a KiCad .lib file that contains
the definition of the connector. In current
practice I treat that .lib file as being temporary,
because I then use KiCad's symbol-library editor to
"import" that symbol from that .lib file into the
"AGC_DSKY" symbol library, and then delete the .lib
file itself. <a
href="https://github.com/virtualagc/virtualagc/tree/schematics#connectors">See
also the explanation of connectors in the README</a>.<a
href="https://github.com/virtualagc/virtualagc/blob/schematics/Scripts/MakeConnector.py"><br>
</a></td>
</tr>
<tr>
<td valign="middle">MakeDualNorLib.py</td>
<td valign="middle">Creation of custom KiCad
schematic-symbol libraries for NOR gates.</td>
<td valign="middle"><a
href="https://github.com/virtualagc/virtualagc/blob/schematics/Scripts/MakeDualNorLib.py">As
far as how to specify the NOR gate library to be
created, see the comments within the code itself</a>.
Most variations relate to the (hardcoded) power-supply
and return signal names, though there are additional
configurable items such as expander vs non-expander,
display of pin numbers vs no display of pin numbers,
numerical pin numbers vs alphabetical pin numbers, and
Block II vs Block I vs ND-1021041. What the
program actually creates is a KiCad library containing
all parts of the multipart symbol, in all variations
of ordering of input pins (including missing pins,
which are tied to the power-supply return). The
only configuration omitted is that of no input pins —
i.e., of all input pins being tied to ground.
(An oversight on my part.) The library itself
should simply be retained permanently <a
href="https://github.com/virtualagc/virtualagc/tree/schematics/Schematics/1006061C">along
with the other libraries</a>, and is typically named
according to the pattern D3NOR-<i>VCC</i>-<i>GND</i>[-<i>OPTIONS</i>].lib.
<a
href="https://github.com/virtualagc/virtualagc/tree/schematics#cad-system">See
also the explanation about libraries in the README</a>,
and <a
href="https://github.com/virtualagc/virtualagc/tree/schematics#nor-gates">the
discussion of NOR gates as well</a>.<a
href="https://github.com/virtualagc/virtualagc/blob/schematics/Scripts/MakeDualNorLib.py">
</a></td>
</tr>
<tr>
<td valign="middle">autoplaceKiCad.py</td>
<td valign="middle">Semi-automated placement of
connector-pad and NOR-gate symbols into KiCad
schematics.<br>
</td>
<td valign="middle"><a
href="ElectroMechanical.html#Program:_autoplaceKiCad.py">See
the extended discussion below<br>
</a></td>
</tr>
<tr>
<td valign="middle">printKiCad.sh</td>
<td valign="middle">Creation of PNG images of KiCad
schematic sheets.</td>
<td valign="middle">Requires <a
href="https://www.gnu.org/software/bash/">bash</a>
(or similar), <a
href="https://www.gnu.org/software/sed/">sed</a>,
and <a href="https://imagemagick.org/index.php">ImageMagick</a>.
The schematic sheet is first "plotted" to Postscript
format in the KiCad schematic editor, and then the
script is run to convert Postscript to PNG. Any
number of Postscript plots can be specified at the
script's command line. The functioning of the
script is quite simple: It uses sed to
stylistically correct dashed lines (whose unalterable
pitch in KiCad is not consistent with the large
physical dimensions of G&N sheets), and then uses
ImageMagick to convert the corrected Postscript to
PNG. <a
href="https://github.com/virtualagc/virtualagc/tree/schematics#printing-from-kicad">See
also the explanation of printing in the README</a>.<br>
</td>
</tr>
<tr>
<td valign="middle">blockAnnotater.py</td>
<td valign="middle">Semi-automated correction of
reference designators in KiCad hierarchical schematics
to agree with G&N engineering drawings.<br>
</td>
<td valign="middle"><a
href="ElectroMechanical.html#Program:_blockAnnotater.py">See
the extended discussion below<br>
</a></td>
</tr>
<tr>
<td valign="middle">eelint.awk</td>
<td valign="middle">Semi-automated correction of
artifacts in KiCad schematics, such as wires that are
not quite horizontal/vertical or which have short jogs
in them.</td>
<td valign="middle"><a
href="ElectroMechanical.html#Program:_eelint.awk">See
the extended discussion below<br>
</a></td>
</tr>
<tr>
<td valign="middle">listConnectors.awk</td>
<td valign="middle">Generation of list of captioned
connector pads from a KiCad schematic.<br>
</td>
<td valign="middle">See comments in <a
href="https://github.com/virtualagc/virtualagc/blob/schematics/Scripts/listConnectors.awk">listConnectors.awk</a>,
<a
href="https://github.com/virtualagc/virtualagc/blob/schematics/Scripts/listConnectors.sh">listConnectors.sh</a>,
and <a
href="https://github.com/virtualagc/virtualagc/blob/schematics/Scripts/listConnectorsAllModules.sh">listConnectorsAllModules.sh</a><br>
</td>
</tr>
<tr align="center">
<td colspan="3" rowspan="1" valign="middle"><i>Context:
Verilog-based simulation of Block II AGC electrical
schematics.<br>
</i></td>
</tr>
<tr>
<td valign="middle">pins.txt</td>
<td valign="middle">Database of Block II AGC backplane
signals<br>
</td>
<td valign="middle">This is created by opening <a
href="https://github.com/virtualagc/agc_hardware/blob/block2/delphi.db">Mike
Stewart's pin database</a> in <a
href="https://www.sqlite.org/index.html">sqlite</a>,
and dumping it in CSV format. The options required
are: Space as field delimiter, no quotes around
fields, no header line for field names.<br>
</td>
</tr>
<tr>
<td valign="middle">bin_to_verilog.py<br>
</td>
<td valign="middle">TBD</td>
<td valign="middle">TBD</td>
</tr>
<tr>
<td valign="middle">dumbInitialization.py</td>
<td valign="middle">Creation of a set of flip-flop
initializations.<br>
</td>
<td valign="middle"><a
href="Verilog.html#Generating_Flip-flop_Initialization">See
the Appendix of the digital-simulation page</a><br>
</td>
</tr>
<tr>
<td valign="middle">dumbTestbench.py</td>
<td valign="middle">Creation of a Verilog test-bench
file.<br>
</td>
<td valign="middle"><a
href="http://Verilog.html#Converting_Verilog_Module_to_Verilog">See
the Appendix of the digial-simulation-page</a><br>
</td>
</tr>
<tr>
<td valign="middle">dumbVerilog.py</td>
<td valign="middle">Conversion of a logic-flow diagram's
netlist to Verilog.<br>
</td>
<td valign="middle"><a
href="Verilog.html#Converting_Netlist_to_Verilog">See
the Appendix of the digital-simulation page</a><br>
</td>
</tr>
<tr>
<td valign="middle">extractInstructionsFromTIM.awk</td>
<td valign="middle">TBD</td>
<td valign="middle">TBD</td>
</tr>
<tr>
<td valign="middle">extractMikeGates.awk</td>
<td valign="middle">TBD</td>
<td valign="middle">TBD</td>
</tr>
<tr>
<td valign="middle">instruction_trans_decoder.py</td>
<td valign="middle">TBD</td>
<td valign="middle">TBD</td>
</tr>
<tr>
<td valign="middle">makeGateTranslate.sh</td>
<td valign="middle">TBD</td>
<td valign="middle">TBD</td>
</tr>
<tr>
<td valign="middle">netlisterOP2.py</td>
<td valign="middle">TBD</td>
<td valign="middle">TBD</td>
</tr>
<tr>
<td valign="middle">pooh.py (plus normalizedMikeNets.py)</td>
<td valign="middle">TBD</td>
<td valign="middle">TBD</td>
</tr>
<tr align="center">
<td colspan="3" rowspan="1" valign="middle"><i>Context:
Verilog-based simulation of Block I AGC electrical
schematics</i></td>
</tr>
<tr>
<td valign="middle">pinsBlockI.txt</td>
<td valign="middle">TBD</td>
<td valign="middle">TBD</td>
</tr>
<tr>
<td valign="middle">pinsDbBlockI.awk</td>
<td valign="middle">TBD</td>
<td valign="middle">TBD</td>
</tr>
<tr align="center">
<td colspan="3" rowspan="1" valign="middle"><i>Context:
Customization of engineering-drawing search engine:</i></td>
</tr>
<tr>
<td valign="middle">tipuesearch.js</td>
<td valign="middle">The principal code for the
engineering-drawing search engine.<br>
</td>
<td valign="middle">This code came from <a
href="http://www.tipue.com/search/">Tipue Search</a>,
but has been modified to provide customized formatting
for search results, and could be additionally or
alternately customized for offline usage. <a
href="https://github.com/virtualagc/virtualagc/blob/gh-pages/TipueSearch/tipuesearch.js">The
code itself is here</a>.<br>
</td>
</tr>
<tr>
<td valign="middle">tipuesearch_content.js</td>
<td valign="middle">The master engineering-drawing
database in JSON format.<br>
</td>
<td valign="middle">Probably the only non-obvious thing
thing is that in URLs, the substrings of the form @<i>N</i>@
need to be replaced by prefixes[<i>N</i>]. <a
href="https://github.com/virtualagc/virtualagc/blob/gh-pages/TipueSearch/tipuesearch_content.js">The
code itself is here</a>.<br>
</td>
</tr>
<tr>
<td valign="middle">AgcDrawingIndex.py<br>
MakeTipueSearch.py<br>
</td>
<td valign="middle">Creates the engineering-drawing
database from index pages (HTML) on the website.<br>
</td>
<td valign="middle">Creation of the master
engineering-drawing database is a two-step process, in
which the AgcDrawingIndex<i>XXXX</i>.html pages from
the Virtual AGC website are processed first by
AgcDrawingIndex.py and then by
MakeTipueSearch.py. For more information, refer
to the comments in <a
href="https://github.com/virtualagc/virtualagc/blob/schematics/Scripts/AgcDrawingIndex.py">the
AgcDrawingIndex.py source code</a>.<br>
</td>
</tr>
<tr>
<td valign="middle">unpunch.py</td>
<td valign="middle">Extracts metadata and renames
scanned G&N engineering drawings scanned from
aperture cards at NARA SW.<br>
</td>
<td valign="middle">This would be useful only to someone
who had access to raw scans of boxes of aperture
cards. The code is specific to aperture cards in
which the punched metadata conforms to the
marking-format printed on the cards themselves (or at
least the ones I've seen). G&N drawings in
box range 430-470 (MIT, AC Electronics, Kollsman,
...); I cannot speak for other ranges, but North
American Aviation boxes do <i>not</i> conform.
Nevertheless, the idea behind unpunch.py is sound, so
if it were altered to a different formatting pattern
it could be useful for it as well. <a
href="https://github.com/virtualagc/virtualagc/blob/schematics/Scripts/unpunch.py">See
the extensive comments in the code itself.</a><br>
</td>
</tr>
</tbody>
</table>
<br>
<h2><a name="Program:_autoplaceKiCad.py"></a>Program:
autoplaceKiCad.py</h2>
<p>This program assists in semi-automatically placing
connector pads and NOR-gate symbols into a KiCad
schematic. It is used if you are transcribing a
G&N "logic-flow diagram" into KiCad. <a
href="https://github.com/virtualagc/virtualagc/blob/schematics/Scripts/autoplaceKiCad.py">The
code itself is here</a>.<br>
</p>
<p>In creating a CAD transcription of a G&N "logic-flow"
diagram, manual choice of the appropriate connector and
NOR-gate library symbols within the KiCad schematic editor
(which is called "eeschema") can be quite cumbersome and
time-consuming. The autoplaceKiCad.py program greatly
eases and speeds up this process, in my opinion. As
input, the user provides a text file that:<br>
</p>
<ul>
<li>Roughly divides the physical area of the schematic
diagram into rectangular blocks.</li>
<li> For each block, provides a <i>textual</i> description
of the connector pads and NOR gates in that block.</li>
</ul>
<p>The program then does a sanity check to expose duplicated
pins or gates, or to find various inconsistencies in pin
numbering, inconsistencies in the way individual NOR gates
must be combined into dual-NOR gates, etc. If those
checks pass, it outputs a KiCad schematic containing nothing
except the specified components. That operation looks
something like this:<br>
</p>
<blockquote>
<p>autoplaceKiCad.py <<i>INPUT</i>.autoplace ><i>OUTPUT</i>.sch<br>
</p>
</blockquote>
<p>The user can then:<br>
</p>
<ol>
<li>Add the component data from <i>OUTPUT</i>.sch to his
own schematic using a single cut-and-pasted operation with
a <i>text editor</i> program. (Don't cut-and-paste
within KiCad itself, or else it will "helpfully" reset all
of the reference designators in the pasted block.)
<i>OUTPUT</i>.sch is a complete, valid schematic, so you
just cut from the first "$Comp" to the last
"$EndComp". I usually paste just prior to the
"$EndSCHEMATC" that appears at the very end the file.<br>
</li>
<li>Edit the now-combined schematic with the KiCad schematic
editor, into the background of which the original scanned
logic-flow diagram has been placed.</li>
<li>Within the schematic editor, manually move each
component where it belongs (relative to the background
image).</li>
</ol>
<p>This may <i>sound</i> like a cumbersome operation (and it
is!), but experience shows pretty conclusively that it is
actually quite a bit faster and far less error-prone than
directly manually adding components within the KiCad
editor. At least for me!<br>
</p>
<p><b>IMPORTANT NOTE:</b> The workflow described above
allows autoplacing a bit of the schematic at a time, rather
than autoplacing all components in one pass. That
temptation should be resisted. Sometimes that
piecemeal approach is appropriate, but you have to be very
careful. The thing you have to be sure of is that both
parts of each dual-NOR are handled in the same autoplacement
pass, because otherwise the program <i>will not </i>be
able to be able to assign the same library symbol to the two
parts. Piecemeal work also bypasses a lot of
consistency checking as well, for things like duplicated
parts. These problems will all be discovered later, of
course, if KiCad's design-rule checker is run, but the
inconsistencies will be a lot harder to fix manually in
KiCad than they would have been in <i>INPUT.</i>autoplace.
So it's safest to just have one big <i>INPUT</i>.autoplace
file and to autoplace all of the components in one
pass. You have been warned!<br>
</p>
<p>Before continuing, I should probably point out that the
scanned image used for the background image in the schematic
editor has to be prepared pretty carefully if you want it to
be maximally useful. For one thing, if a sheet of the
drawing was scanned in several frames, those frames must be
recombined to produce a single unified image. The image must
be scaled correctly; for example, if the original drawing is
"E" size, then the scanned image must be scaled to be
exactly 44"×34". Moreover, it should be
rotated/stretched in such a way that vertical lines are
vertical and horizontal lines are horizontal, and that the <i>inner</i>
boundary of the drawing's border is 0.5" from the edges of
the image. If the full-resolution scanned image is
loaded into the schematic editor, it's probably going to be
quite logy, or perhaps even unusable. So the PPI of
the background image should probably be changed (whilst
preserving the correct physical dimensions!) as low as you
can stand. Typically, I use 50 PPI, but on some
occasions have gone as low as 20 PPI. I won't trouble
you with exact details how to perform each of these
steps. Rather than loading the background image
scan into the schematic file, it is actually loaded into the
KiCad "template" (*.wks) file for the design, using KiCad's
worksheet editor program. (And <i>removed</i> from it
prior to committing anything to GitHub, please since the
template file will now be enormous!)<br>
</p>
<p>In its simplest form, <i>INPUT</i>.autoplace looks
something like this:<br>
</p>
<blockquote>
<p><tt>W= <i>width<br>
</i>L <i>x y</i><br>
J <i>pin1</i><br>
J <i>pin2</i><br>
J <i>pin3</i><br>
...<br>
N <i>gate1 loc1 </i><i>a1 b1 c1</i><br>
N <i>gate2 loc2 a2 b2 c2</i><br>
...<br>
</tt></p>
</blockquote>
This defines a single rectangular block on the schematic, <tt><i>width</i></tt>
inches wide, with an upper left-hand corner located <tt><i>x</i></tt><tt>,</tt><tt><i>y</i></tt>
inches from the upper-left corner of the schematic. In <i>OUTPUT</i>.sch,
the placed component will appear in rows starting at the top
of this block and working downward as each row is filled
up. In other words, it doesn't place the components
exactly where they need to go, but just in the general
vicinity. The <tt>J</tt> and <tt>N</tt> lines
represent symbols to be placed on the schematic, and don't
have to appear in the order shown. Plus, there are other
kinds of symbols the program can add that I haven't put into
the example. These symbol lines can be in any convenient
order, though the most convenient order in terms of moving the
symbols to their proper locations later are going to involved
sweeping through the block row-wise, from left to right.<br>
<br>
<img alt="" src="sampleGates.png" width="335" height="282"
align="right">Each <tt>J</tt> line represents a connector
pin (an oval pad) with the associated pin number (<i>pin1</i>,
<i>pin2</i>, or <i>pin3</i> in the example shown). <br>
<br>
Similarly, each <tt>N</tt> line represents half of a dual
3-input NOR gate. The associated gate number (<i>gate1</i>
or <i>gate2</i> in the example) is a 5-digit number written
directly on the gate in G&N logic-flow diagrams.
Similarly, the location number (loc1 or loc2) is a 2-digit
number written directly on the gate in the diagram. The
gate numbers are all unique, and no specific gate number can
recur. However, the location numbers relate to the chip
rather than the gate, and since the chips are dual-NORs, each
location number actually appears twice, with two different
associated gate number. <br>
<br>
Because these are triple-input NOR-gates, each has 3
inputs. For the "A" half of the dual-NOR, the pins are
labeled A, B, or C, while for the "B" half they are labeled D,
E, or F. Thus the pin numbers ("<i>a1 b1 c1</i>" or "<i>a2 b2
c2</i>" in the example) are "A B C" or "D E F" ... but not
really! The original schematics were drawn very
flexibly, so that the pins might actually be in other orders,
such as "B A C" or "C B A". But more than that, the pins
might be omitted completely in the drawing, with any missing
pin implicitly being grounded. We represent missing pins
as ";" or "_", so "<i>a1 b1 c1</i>" could actually be "_ A _"
or "C B _". (When I created the symbol libraries and
autoplaceKiCad.py, I neglected to consider that <i>all</i>
the input pins might be grounded, "_ _ _", so I don't
provide for that case.)<br>
<br>
In terms of actual numbers, therefore, our example <i>INPUT</i>.autoplace
could perhaps be:<br>
<blockquote><tt>W= 10</tt><br>
<tt><i> </i>L 13.5 1.2</tt><br>
<tt> J 153</tt><br>
<tt> J 154</tt><br>
<tt> J 155</tt><br>
<tt> ...</tt><br>
<tt> N 38125 40 F E D</tt><br>
<tt> N 38126 41 F _ E</tt><br>
<tt> ...</tt><br>
</blockquote>
But this just scratches the surface. In no particular
order, here are some of the other variants that can be briefly
described:<br>
<ul>
<li>Blank lines or comments (prefixed with "#") are ignored.<br>
</li>
<li>Multiple "<tt>W=</tt>"/"<tt>L x y</tt>" blocks can
appear in the file, thus tiling the sheet into rectangular
blocks, of possibly differing sizes/shapes.<br>
</li>
<li><tt>J</tt> lines represent connector pads (visually,
ovals wider than their height) with the wires exiting to
the <i>right</i>. There are also <tt>j</tt> lines,
also connector pads, in which the wires exit to the <i>left</i>.
Similarly, the wires on <tt>K</tt> pads exit to the <i>bottom</i>
and those of <tt>k</tt> pads to the <i>top</i>.</li>
<li><tt>J</tt>, <tt>j</tt>, <tt>K</tt>, <tt>k</tt> lines
can also have from 1 to 4 optional symbolic labels
representing associated backplane signal names. For
example, "<tt>j 153 F12B</tt>".</li>
<li>Rather than an <tt>N</tt> line, you could use an <tt>X</tt>
line ... which acts the same but specifies an "expander"
NOR gate rather than a normal NOR gate.</li>
<li><img alt="" src="sampleNodesArrow.png" width="332"
height="178" align="right">There are also <tt>O</tt>
lines ("oh", not "zero"), not shown in the example, of the
form "<tt>O netname</tt>", such as "<tt>O DAS0/</tt>".
These place a symbol having just one pin (exiting to the <i>right</i>)
that looks like a small open circle with a label next to
it. This is a common way to represent intrasheet
connections in G&N schematics.</li>
<li>There are also <tt>A</tt> lines, not shown, of the form
"<tt>A <i>digits</i></tt>", such as "<tt>A 1</tt>".
These place a symbol that looks like an up-arrow with a
number (<tt><i>digits</i></tt>) in parenthesis above
it. It has no electrical function, but is used in
some G&N schematics to indicate how many other points
in the schematic sheet are implicitly electrically
connected to it, as opposed to being directly connected by
a visual wire. Those other connections are the <tt>O</tt>
lines mentioned above. Since the associated
schematic symbols do not actually enforce any electrical
connectivity between the two points, it is necessary to
manually add matching KiCad netnames to the wires
associated with the symbols for the <tt>O</tt> and <tt>A</tt>
lines. That is done in the KiCad editor rather than
in the <i>INPUT</i>.autoplace file. <br>
</li>
<li>If the 2nd field in a <tt>J</tt> or <tt>N</tt> line is
".", then the pad number, gate number, or location number
simply autoincrements. Note that autoincrementing
connector-pad numbers remain in the ranges <i>Nnn</i>
where <i>nn</i> is 01-20, 22-50, or 52-71 (as would be
required for Block II AGC logic modules).
Incidentally, for Block II, the format of such an <tt>N</tt>
line changes to "<tt>N . <i>n</i></tt>", where <tt><i>n</i></tt>
is 1, 2, or 3, and is simply the number of input pins.</li>
<li>In addition to <tt>N</tt> and <tt>X</tt> lines, it is
also possible though rare to have otherwise-similar lines
that instead begin with <tt>N1</tt>, <tt>N2</tt>, <tt>N3</tt>,
<tt>N4</tt>, <tt>X1</tt>, <tt>X2</tt>, <tt>X3</tt>, or
<tt>X4</tt>. This is discussed along with the
general "<tt>N=</tt>" directive below.<br>
</li>
</ul>
Various options can be added to the autoplace file to modify
this basic behavior. Each option appears on a line by
itself, and they are typically grouped at the top of the file,
prior to any of the "<tt>L x y</tt>" lines. Not all of
these options have been designed to work in cooperation with
each other. Here are the currently-available ones;
they're shown in quotes for clarity, but the quotes aren't
used in the actual input files:<br>
<ul>
<li>General:</li>
<ul>
<li>"<tt>G= <i>start</i></tt>". Changes the default
starting point (0) for autoincrementing NOR-gate numbers
in <tt>N</tt> lines to <i><tt>start</tt></i>.</li>
<li>"<tt>P= <i>start</i></tt>". Sets the starting
number for autoincrementing connector pads (defaults to
1).</li>
<li>"<tt>N= <i>symbol refd</i></tt>" (and <tt>N1=</tt>,
<tt>N2=</tt>, <tt>N3=</tt>, <tt>N4=</tt>). Sets
the schematic-symbol library name (<i><tt>symbol</tt></i>)
and the reference designator prefix (<tt><i>refd</i></tt>)
used when placing NOR-gates onto the schematic.
The available NOR-gate symbol libraries are named
D3NOR-*.lib, and any path or filename extension is
omitted in <tt><i>symbol</i></tt>. The reference
designator for any individual NOR-gate is automatically
formed by prefixing <tt><i>refd</i></tt> to the gate's
2-digit location code, and <tt><i>refd</i></tt> will be
something like "U1", "U2", "U3", or "U4"; thus, the
resulting reference designators will typically be of the
form U + 3 digits. This scheme is based on the way
the sheets of a typical G&N logic-flow diagram are
structured, in that <i>each</i> of the sheets will have
2-digit location codes in the range 01-30, so that it is
necessary to have unique prefixes for each sheet to make
sure that reference designators are unique as
well. Note, by the way, that an "<tt>N=</tt>"
directive applies to the <i>entire</i> set of <tt>N</tt>
lines in INPUT.autoplace, and not just to the ones that
ones that follow it. Sometimes, though rarely, not
all NOR-gates on a given sheet come from the same symbol
library. Sometimes also, though even more rarely,
a schematic will have a single sheet in which a
combination of U1<i>nn</i>, U2<i>nn</i>, U3<i>nn</i>,
and U4<i>nn</i> reference designators appear on the same
schematic sheet. Neither of these latter two rare
cases can be implemented using <tt>N</tt> and <tt>N=</tt>
lines as just described. For those cases, <tt>N1</tt>,
<tt>N2</tt>, <tt>N3</tt>, and <tt>N4</tt> lines are
provided. They work exactly like <tt>N</tt>
lines, but essentially provided non-overlapping
"namespaces" — i.e., they allow the use of independent
library symbols and reference-designator prefixes by
means of their own directives "<tt>N1= <i>symbol refd</i></tt>",
"<tt>N2= <i>symbol refd</i></tt>", "<tt>N3= <i>symbol
refd</i></tt>", and "<tt>N4= <i>symbol refd</i></tt>".</li>
<li>"<tt>X= <i>symbol refd</i></tt>" (and <tt>X1=</tt>,
<tt>X2=</tt>, <tt>X3=</tt>, <tt>X4=</tt>). Same
as above, but for expander NOR-gates.<br>
</li>
</ul>
<li>Specific to Block II:</li>
<ul>
<li>"<tt>module= <i>moduletype</i></tt>". This
option is <i>primarily</i> used to modify how reference
designators are chosen for connector pads, based on the
pin numbers. The choices for <i><tt>moduletype</tt></i>
are <tt>A52</tt>, <tt>B1</tt>, and <tt>B</tt>, and
the interpretations are: <br>
</li>
<ul>
<li>By default, if this option isn't used at all,
connector-pad numbers 101-171 select reference
designator J1 (symbol "ConnectorA1-100" in symbol
library AGC_DSKY), 201-271 select J2
("ConnectorA1-200"), 301-371 select J3
("ConnectorA1-300"), and 401-471 select J4
("ConnectorA1-400"), which is suitable for all Block
II AGC logic modules.</li>
<li><tt>B1</tt>: Suitable for modules with pinouts
like module B1, namely pads 101-124 select J1
("ConnectorB1-100"), 201-224 select J2
("ConnectorB1-200"), 301-324 select J3
("ConnectorB1-300"), and 401-424 select J4
("ConnectorB1-400").</li>
<li><tt>B</tt>: Connector pads 101-169 select J1
("ConnectorB8-100") and 201-269 select J2
("ConnectorB8-200").</li>
<li><tt>A52</tt>: J1 ("ConnectorA52"). This
also has the side effect of changing the NOR-gate
pin-numbers to "2", "3", "4", "6", "7", "8" (and "_"
or ";").</li>
</ul>
<li>"<tt>full71</tt>". As mentioned above, the
default connector type used in the absence of a "<tt>module=</tt>"
directive, is appropriate for a Block II AGC logic
module: 4 rows of 71 pins each, with the 21st and
51st pins of each row removed. If <tt>full71</tt>
is used, the missing 21st and 51st pins are restored to
the default (by instead using library symbols
"Connector-100", "Connector-200", "Connector-300", and
"Connector-400").</li>
<li>"<tt>GP= <i>prefix</i></tt>". As explained
above, in each <tt>N</tt> or <tt>X</tt> line, the
NOR-gate has a 5-digit "gate number" associated with
it. If the leading digits are always the
same — or indeed, if they are not all <i>digits</i>
— then this directive can be used to specify what the
leading characters are. It is then only necessary
to enter the remaining digits within the <tt>N</tt> or
<tt>X</tt> line, and the prefixed characters bypass the
sanity check. For example, a gate number of
"6_123" would be illegal if appearing directly in an <tt>N</tt>
or <tt>X</tt> line, because it doesn't consist entirely
of digits. However if "<tt>GP= 6_</tt>" were used,
then just "123" would used as the gate number in the <tt>N</tt>
or <tt>X</tt> line. The resulting gate number
would still be "6_123", but the result would now be
legal. To use this approach, however, <i>all</i>
of the gate numbers would begin with "6_".</li>
<li>"<tt>noloc</tt>". If this directive used, then
the 2-digit location numbers are not visible on the NOR
gates. They are still present, but simply marked
internally as being invisible, and can be accessed or
visually restored by editing the NOR gate within KiCad.<br>
</li>
<ul>
</ul>
<ul>
</ul>
</ul>
<li>Specific to Block I:<br>
</li>
<ul>
<li><img alt="" src="sampleShadow1.png" width="248"
height="183" align="right">"<tt>block1</tt>".
Indicates an official Block I drawing. In such
circuits, the chips have one NOR-gate each (rather than
two), and the input pins are "1", "3", "5" (and "_" or
";" if missing) rather than "A", "B", "C", "D", "E",
"F". Moreover, there were two separate
implementations of the circuits, referred to as AGC4 and
AGC5, resulting in two separate NOR-gate gate codes and
two separate pin numbers for each backplane-connector
pad. The formats in <i>INPUT</i>.autoplace were
altered accordingly: "<tt>N <i>loc gateAGC4
gateAGC5 pin1 pin2 pin3</i></tt>" and "<tt>J <i>pinAGC4
pinAGC5 signal</i></tt>". The AGC5 gate codes
are the usual 5-digit numbers, but the AGC4 gate codes
are like "1F4" or "2D3".</li>
<li>"<tt>shadow1</tt>". Implies and depends on "<tt>block1</tt>".
If present, connector pads (<tt>J</tt> lines) are
automatically supplemented by an additional connector
pad of identical appearance (but no electrical function)
but having a dotted outline. Such pads are used in
some Block I logic flow diagrams to indicate alternate
backplane signals.</li>
<li>"<tt>mirror1</tt>". Implies and depends on "<tt>shadow1</tt>"
and "<tt>block1</tt>". Reverses the pin numbering
(assuming a 142-pin connector) between a <tt>J</tt>
connector pad and its shadow.<br>
</li>
<li>"<tt>nd1021041</tt>". Overrides "<tt>block1</tt>".
This is used for schematics recovered from Block I
descriptive document ND-1021041, which have various
differences stylistically from the official
drawings. Moreover, there are no 2-digit location
numbers for NOR-gates in ND-1021041, so <tt>N</tt>
lines become just "<tt>N <i>gate a b c</i></tt>".</li>
<li>"<tt>bit</tt>". Uses 3-digit gate numbers rather
than 5-digit ones, and automatically prefixes them with
"xx". This is for schematics of a module that can
be plugged into 16 different backplane slots, and in
practice applies only to Block I logic modules
A1-A16. If used, then <tt>J</tt> lines have 16
backplane-signal labels rather than the limit of 4
mentioned earlier. However, these labels are
internal to the CAD and not displayed on the schematic.</li>
<li>"<tt>dupej</tt>". Some Block I drawings have
duplicate connector pads with identical pin
numbers. This not allowed in KiCad, so normally it
would be flagged as a fatal error by
autoplaceKiCad.py. There are various non-fatal
ways to handle such cases. One way is the "<tt>dupej</tt>"
option. If used, whenever a duplicated <tt>J</tt>
line is found, the 2nd instance an onward are replaced
electrically by <tt>O</tt> lines.<br>
</li>
</ul>
</ul>
<h2><a name="Program:_blockAnnotater.py"></a>Program:
blockAnnotater.py</h2>
<p><a
href="https://github.com/virtualagc/virtualagc/tree/schematics#organization-of-drawings-into-reusable-blocks">Also
see the explanation of reusable circuit blocks in the
README file</a>.<br>
</p>
<p>In transcribing Apollo G&N electrical schematics to
CAD, we want all component reference designators to match
those used in the G&N engineering drawings, and we
particularly want reference designators appearing in
netlists and electrical simulations to be accurate with
respect to the original drawings. This is not a
problem for most transcribed drawings but becomes a problem
for some schematics of analog circuitry in which the circuit
comprises hierarchical blocks which appear in multiple
instances. For example, suppose the main circuit had a
block (let's call it block "P") which is used 5 times.
In KiCad, the natural way to deal with this is a process
called "annotation", in which KiCad assigns distinct
reference designators to each component appearing in each
instance of block "P". Natural or not, the rules
applied by KiCad do not correspond to the reference
designators in the G&N engineering drawings
themselves. For example, if there were a resistor that
we had called R3 in block "P", KiCad might annotate those 5
instances of the resistor as R3, R101, R201, R301, and R401,
whereas the G&N drawings might refer to them as 1R3,
2R3, 3R3, 4R3, and 5R3. The latter, of course, is what
we <i>want</i>.<br>
</p>
<p>Working around this problem involves a semi-automated
process with several steps:<br>
</p>
<ol>
<li><img alt="" src="sampleBaseRefd.png" width="366"
height="339" align="right">In the top-level drawing, the
hierarchical blocks with multiple instances have to be
given sheet names corresponding to the prefixes attached
to the reference designators in them. <i>Usually</i>,
these will be sheet names "1", "2", "3", and so on.
In fact, blockAnnotater.py will strip any suffixed
non-digit characters from the sheet names, as well as
certain prefixes ("--", "xx", "XX") so sheet names like
"1P" or "xx5Q" can be used just as easily as "1" or "5",
if necessary to more-closely match the appearance of the
original drawings. As for where these numerical
prefixes come from, they cannot be deduced from the
schematics, but instead have to be pulled from associated
engineering drawings for the assembly containing the
circuit, such as from <a
href="https://archive.org/stream/apertureCardBox459NARASW_images/apertureCardBox459NARASW#page/n1277/mode/1up">photographic
masters of insulators</a>, <a
href="https://archive.org/stream/apertureCardBox462NARASW_images#page/n806/mode/1up">wiring
boards</a>, etc.<br>
</li>
<li>In the reusable circuit blocks, using the KiCad
schematic editor, edit each component, as follows:</li>
<ul>
<li>Add a new field called "baseRefd". Mark it as
visible, and assing its value as the reference
designator as shown in the original engineering drawing.<br>
</li>
</ul>
<ul>
<li>Mark its actual reference-designator field as
invisible. Or alternately, perhaps preferably in
some ways, leave it visible but assign it a smaller font
size and move it close to the visible location of the
baseRefd field so that it is clearly subordinate to
it. The image to the right illustrates the latter
alternative; in it, markings like Q5 and R13 are the
baseRefd field, whereas those like 1Q5 and 1R13 are the
true reference designators.<br>
</li>
</ul>
<li> Use KiCad's annotator tool to assign reference
designators to the reusable circuit blocks.</li>
<li>Exit KiCad and use blockAnnotater.py to reassign the
reference designators which KiCad just assigned.</li>
</ol>
<p>The actual reference designators assigned in the reusable
blocks by blockAnnotator.py are <br>
</p>
<div align="center">(prefix derived from parent sheet name)
concatenated to (child component baseRefd)<br>
</div>
<p>This is the appropriate formula in most cases, but there
are a few cases in which the prefixes derived from the
parent sheet name simply don't correspond to the
chile-component prefixes in the engineering drawings.
A numerical offset can be defined that changes the formula
instead to<br>
</p>
<p align="center">(prefix derived from parent sheet name +
numerical offset) concatenated to (child component baseRefd)</p>
<p>(Notice that the "+" is meant to be a numerical
addition.) The way this is done is by tweaking one of
the 4 comment fields of the child schematic. If any of
these comments is changed to<br>
</p>
<div align="center">NumberFrom=<i>N</i><br>
</div>
<p>then <i>N</i> is used as a numerical offset to the
component prefixes within that child block.<br>
</p>
<p>At present, only two levels of drawings (parent + child)
are supported, and this has proven sufficient for all
G&N schematics encountered so far. If any
three-level drawings (parent + child + grandchild) are ever
discovered, the software will need to be reworked.<br>
</p>
<p>Regarding the two different options listed above as to how
to treat components' true reference-designator fields, both
options have arguments in their favor. If the true
reference designators are made invisible, the schematics
(and in particular their PNG renderings) will look just like
the original drawings. On the other hand, particularly
in editing the CAD files, it obscures the fact that the
markings shown are <i>not</i> the true reference
designators, as well as obscuring the fact that the
different instances of the block have different reference
designators. The choice as to whether or not to
display the true reference designators is therefore
partially a question of personal aesthetics.<br>
</p>
<p>Actual details of usage and additional documentation can be
found in <a
href="https://github.com/virtualagc/virtualagc/blob/schematics/Scripts/blockAnnotater.py">the
blockAnnotater.py source code</a>.<br>
</p>
<h2><a name="Program:_eelint.awk"></a>Program:
eelint.awk</h2>
<p>In manually editing G&N schematics in KiCad's schematic
editor — and in particular, in adapting an existing CAD file
for a different but similar version of the circuit — it's
extremely easy to leave it littered with junky-looking
constructs such as:<br>
</p>
<ul>
<li>Items not aligned to the 25-mil grid we use for G&N
drawings.</li>
<li> Wires with a tiny inclination to exact horizontal or
vertical.</li>
<li>Wires with tiny jogs in them.</li>
<li>Stray, short wires attached electrically at one end but
dangling from the other, sometimes causing spurious
junctions (fat dots) to appear.</li>
</ul>
<p>The program eelint.awk analyzes a schematic to find such
problems. In its simplest form, the program is run as
follows:<br>
</p>
<div align="center">awk -f eelink.awk <i>INPUT</i>.sch <i>INPUT</i>.sch
><i>OUTPUT</i>.sch<br>
<div align="left"><br>
Yes, the input schematic does appear twice on the command
line, and it is not a typo. The script outputs error
messages about the problems it has found to stderr, and
outputs a completely new schematic file to <i>OUTPUT</i>.sch
to stdout. The input file is not changed at
all. If there are no error messages, then the output
file should be the same as the original and can simply be
ignored. <br>
<br>
However, if errors are found, then the output file will be
like the original but with the addition of markers that
have been inserted where the errors are thought to
be. If <i>OUTPUT</i>.sch is edited in KiCad, you
can simply do a text search for "eelint" (which is the
name of the marker symbol that has been inserted).
The idea is that you find all of these markers, manually
edit away the problems, then remove the markers.
Once you're satisfied, OUTPUT.sch can simply be "saved as"
with the original file's name. Obviously, there's a
danger here of overwriting the wrong thing, so care is
required.<br>
<br>
Consult <a
href="https://github.com/virtualagc/virtualagc/blob/schematics/Scripts/eelint.awk">the
source code</a> for additional instructions and info.<br>
</div>
</div>
<ul>
</ul>
</div>
</div>
<h1> </h1>
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